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fujitsu semiconductor controller manual f 2 mc-8l 8-bit microcontroller mb89570 series hardware manual cm25-10140-1e

fujitsu limited f 2 mc-8l 8-bit microcontroller mb89570 series hardware manual

i preface n purpose and intended reader of this manual the mb89570 series is a product developed as one of the 8-bit microcontroller general-purpose versions of f 2 mc-8l family is battery controlled applications using sm bus. this series can be used widely for devices from consumer products to industrial equipment. this manual describes the functions and operations of the mb89570 series for engineers who develop products using microcontrollers of the mb89570 series. for details on various instruction sets used, see "f 2 mc-8l programming manual". n trademark f 2 mc is the abbreviation of fujitsu flexible microcontroller. other system and product names in this manual are trademarks of respective companies or organizations. the symbols ? and ? are sometimes omitted in this manual. n the i 2 c licence purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
ii n organization of this manual this manual is organized into the following 19 chapters. chapter1 "overview" this chapter describes the features and basic specifications of the mb89570 series. chapter2 "handling device" this chapter describes the precautions to be taken when using the mb89570 series. chapter3 "cpu" this chapter describes the functions and operations of the cpu. chapter4 "i/o port" this chapter describes the functions and operations of the i/o port. chapter5 "timebase timer" this chapter describes the functions and operations of the timebase timer. chapter6 "watchdog timer" this chapter describes the functions and operations of the watchdog timer. chapter7 "watch prescaler" this chapter describes the functions and operations of the watch prescaler. chapter8 "8/16-bit timer/counter" this chapter describes the functions and operations of the 8/16-bit timer/counter. chapter9 "16-bit timer/counter" this chapter describes the functions and operations of the 16-bit timer/counter. chapter10 "external interrupts (edges)" this chapter describes the functions and operations of the external interrupt circuit (edge). chapter11 "a/d converter" this chapter describes the functions and operations of the a/d converter. chapter12 "d/a converter" this chapter describes the functions and operations of the d/a converter. chapter13 "comparator" this chapter describes the functions and operations of the comparator. chapter14 "uart/sio" this chapter describes the functions and operations of the uart/sio. chapter15 "i 2 c" this chapter describes the functions and operations of the i 2 c. chapter16 "multi-address i 2 c" this chapter describes the functions and operations of the multi-address i 2 c. chapter17 "bridge circuit" this chapter describes the functions and operations of a bridge circuit.
iii chapter18 "lcd controller/driver" this chapter describes the functions and operations of the lcd controller/driver. chapter19 "wild register function" this chapter describes the functions and operations of the wild register function. "appendix" his appendix includes i/o maps, instruction lists, and other information.
iv ? 2001 fujitsu limited printed in japan 1. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. 2. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 3. the contents of this document may not be reproduced or copied without the permission of fujitsu, ltd. 4. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 5. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. 6. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.
v reading this manual n notations of the register name and pin name m notations of the register name and bit name m notations of a double-purpose pin p10/an5 pin some pins can be used by switching their functions using, for example, settings by a program. each double-purpose pin is represented by separating the name of each function using "/". by writing "1" into the "sleep bit" (stbc: slp) of the standby control register, register name bit abbreviation bit abbreviation bit abbreviation register abbreviation register abbreviation register abbreviation bit name prohibit (tbtc: tbie=0) the interrupt request output of the timebase timer. data to be set accept an interrupt if the interrupt is permitted (ccr: i=1). current state
vi n documents and development tools required for development items necessary for the development of this product are as follows. to obtain the necessary documents and development tools, contact a company sales representative. m manuals required for development [check field] manuals with the * mark are attached to each product. other manuals, such as those for development, are attached to respective products. software required for development [check field] the type of software product is dependent on the os to be used. for details, see the f 2 mc development tool catalog or product guide. f 2 mc-8l mb89570 series data sheet (provides a table of electrical characteristics and various examples of this product) f 2 mc-8l programming manual (manual including instructions for the f 2 mc-8l family) *fr/f 2 mc family softune c compiler manual (required only if c language is used for development) (manual describing how to develop and activate programs in the c language) *fr/f 2 mc family softune assembler manual for v3 (manual describing program development using the assembler language) *fr/f 2 mc family softune linkage kit manual for v3 (manual describing functions and operations of the assembler, linker, and library manager softune v3 workbench softune v3 for personal ice (required only if the evaluation is performed for the personal-ice) softune v3 for compact ice (required only if the evaluation is performed for the compact-ice)
vii m what is needed for evaluation on the one-time prom microcomputer (if the programming operation is performed at your side) [check field] m development tools [check field] to use a the other development environment, contact respective makers. m references ?"f 2 mc development tool catalog" ? "microcomputer product guide" mb89p579 eprom programmer minato electronics: model-1890a (version 2.5 or later) ou-910 [mos unit] (version 4.32r or later) ml01-891 (3v conversion socket) package conversion adapter rom2-100lqf-32dp-8la (for lqfp) rom2-100tqf2-32dp-8la (for tqfp) mb89pv570 (piggyback/evaluation device) development tool main unit pod probe mb2141a + mb2144-508 mb2144-203
viii
ix contents chapter 1 overview ................................................................................................... 1 1.1 mb89570 series features .................................................................................................... ................. 2 1.2 product lineup in the mb89570 series ....................................................................................... .......... 5 1.3 differences of various product and precautions for selecting the products ......................................... 7 1.4 block diagram of the mb89570 series ........................................................................................ .......... 8 1.5 pin assignment ............................................................................................................. ......................... 9 1.6 package dimensions ......................................................................................................... .................. 10 1.7 pin description ............................................................................................................ ......................... 13 1.8 i/o circuit type ........................................................................................................... ......................... 18 chapter 2 handling device ................................................................................... 23 2.1 notes on handling devices .................................................................................................. ............... 24 chapter 3 cpu ............................................................................................................. 25 3.1 memory space ............................................................................................................... ...................... 26 3.1.1 special areas ............................................................................................................ ..................... 28 3.1.2 storing 16-bit data in memory ............................................................................................ ............ 30 3.2 dedicated registers ........................................................................................................ .................... 32 3.2.1 condition code register (ccr) ............................................................................................ ......... 34 3.2.2 register bank pointer (rp) ............................................................................................... ............. 37 3.3 general-purpose registers .................................................................................................. ................ 38 3.4 interrupts ................................................................................................................. ............................ 40 3.4.1 interrupt level setting registers (ilr1, ilr2, ilr3, ilr4) ............................................................ 42 3.4.2 interrupt processing ..................................................................................................... .................. 44 3.4.3 multiple interrupts ...................................................................................................... ..................... 46 3.4.4 interrupt processing time ................................................................................................ .............. 47 3.4.5 stack operation during interrupt processing .............................................................................. .... 48 3.4.6 stack area for interrupt processing ...................................................................................... .......... 49 3.5 resets ..................................................................................................................... ............................ 50 3.5.1 reset flag register (rsfr) ............................................................................................... ............ 52 3.6 external reset pin ......................................................................................................... ...................... 54 3.6.1 reset operation .......................................................................................................... ................... 55 3.6.2 pin states during reset .................................................................................................. ................ 57 3.7 clock ...................................................................................................................... .............................. 58 3.7.1 clock generator .......................................................................................................... ................... 60 3.7.2 clock controller ......................................................................................................... ..................... 62 3.7.3 system clock control register (sycc) ..................................................................................... .... 64 3.7.4 clock modes .............................................................................................................. ..................... 67 3.7.5 oscillation stabilization wait time ...................................................................................... ........... 70 3.8 standby mode (low power consumption) ....................................................................................... ... 72 3.8.1 operating state in standby mode .......................................................................................... ........ 73 3.8.2 sleep mode ............................................................................................................... ..................... 74 3.8.3 stop mode ................................................................................................................ ...................... 75 3.8.4 watch mode ............................................................................................................... .................... 77
x 3.8.5 standby control register (stbc) .......................................................................................... ........ 78 3.8.6 state transition diagram 1 (dual clock) .................................................................................. ..... 80 3.8.7 notes on using standby mode .............................................................................................. ........ 83 3.9 memory access mode ......................................................................................................... ............... 85 chapter 4 i/o port ..................................................................................................... 87 4.1 overview of the i/o port ................................................................................................... ................... 88 4.2 port 0 ..................................................................................................................... ............................. 91 4.2.1 registers of port 0 (pdr0, ddr0) ......................................................................................... ....... 93 4.2.2 operation of port 0 ...................................................................................................... .................. 94 4.3 port 1 ..................................................................................................................... ............................. 96 4.3.1 registers of the port 1 (pdr1, ddr1) ..................................................................................... ..... 98 4.3.2 operation of the port 1 .................................................................................................. .............. 100 4.4 port 2 ..................................................................................................................... ........................... 102 4.4.1 registers of port 2 (pdr2, ddr2) ......................................................................................... ..... 104 4.4.2 operation of port 2 ...................................................................................................... ................ 106 4.5 port 3 ..................................................................................................................... ........................... 108 4.5.1 register of port 3 (pdr3) ................................................................................................ ............ 111 4.5.2 operation of port 3 ...................................................................................................... ................ 112 4.6 port 4 ..................................................................................................................... ........................... 113 4.6.1 register of port 4 (pdr4) ................................................................................................ ............ 115 4.6.2 operation of port 4 ...................................................................................................... ................. 116 4.7 port 5 ..................................................................................................................... ........................... 117 4.7.1 registers of the port 5 (pdr5, ddr5) ..................................................................................... ... 119 4.7.2 operation of port 5 ...................................................................................................... ................ 121 4.8 port 6 ..................................................................................................................... ........................... 123 4.8.1 register the port 6 (pdr6) ............................................................................................... ........... 125 4.8.2 operation of port 6 ...................................................................................................... ................. 127 4.9 port 7 ..................................................................................................................... ........................... 128 4.9.1 registers of port 7 (pdr7, ddr7) ......................................................................................... ..... 130 4.9.2 operation of port 7 ...................................................................................................... ................ 132 4.10 port 8 .................................................................................................................... ............................ 134 4.10.1 registers of port 8 (pdr8, ddr8) ........................................................................................ ...... 137 4.10.2 operation of port 8 ..................................................................................................... ................. 139 4.11 port 9 .................................................................................................................... ............................ 141 4.11.1 registers of port 9 (pdr9, ddr9) ........................................................................................ ...... 144 4.11.2 operation of port 9 ..................................................................................................... ................. 146 4.12 port a .................................................................................................................... ............................ 148 4.12.1 register of port a (pdra) ............................................................................................... ............ 150 4.12.2 operation of the port a ................................................................................................. ............... 151 4.13 port b .................................................................................................................... ............................ 152 4.13.1 register of port b (pdrb) ............................................................................................... ............ 155 4.13.2 operation of port b ..................................................................................................... ................. 156 4.14 program example of the i/o ports .......................................................................................... .......... 157 chapter 5 timebase timer .................................................................................... 159 5.1 overview of the timebase timer ............................................................................................. ......... 160 5.2 configuration of the timebase timer ........................................................................................ ........ 162
xi 5.3 timebase timer control register (tbtc) ..................................................................................... .... 164 5.4 timebase timer interrupt ................................................................................................... ............... 166 5.5 operation of the timebase timer ............................................................................................ .......... 167 5.6 notes on using the timebase timer .......................................................................................... ....... 169 5.7 program example of the timebase timer ...................................................................................... ... 171 chapter 6 watchdog timer ................................................................................. 173 6.1 overview of the watchdog timer ............................................................................................. ......... 174 6.2 configuration of the watchdog timer ........................................................................................ ........ 175 6.3 watchdog timer control register (wdtc) ..................................................................................... .. 177 6.4 operation of the watchdog timer ............................................................................................ .......... 179 6.5 notes on using the watchdog timer .......................................................................................... ....... 181 6.6 program example of the watchdog timer ...................................................................................... ... 182 chapter 7 watch prescaler .............................................................................. 185 7.1 overview of the watch prescaler ............................................................................................ .......... 186 7.2 configuration of the watch prescaler ....................................................................................... ......... 188 7.3 watch prescaler control register (wpcr) .................................................................................... ... 190 7.4 watch prescaler interrupt .................................................................................................. ................ 192 7.5 operation of the watch prescaler ........................................................................................... ........... 193 7.6 notes on using the watch prescaler ......................................................................................... ........ 195 7.7 program example of the watch prescaler ..................................................................................... .... 196 chapter 8 8/16-bit timer/counter ...................................................................... 199 8.1 overview of the 8/16-bit timer/counter ..................................................................................... ........ 200 8.2 configuration of the 8/16-bit timer/counter ................................................................................ ...... 203 8.3 pins of the 8/16-bit timer/counter ......................................................................................... ............ 205 8.4 registers of the 8/16-bit timer/counter .................................................................................... ......... 207 8.4.1 timer 1 control register (t1cr) .......................................................................................... ........ 208 8.4.2 timer 2 control register (t2cr) .......................................................................................... ........ 211 8.4.3 timer 1 data register (t1dr) ............................................................................................. ......... 214 8.4.4 timer 2 data register (t2dr) ............................................................................................. ......... 216 8.5 8/16-bit timer/counter interrupts .......................................................................................... ............. 218 8.6 operation of the interval timer function ................................................................................... ........ 220 8.7 operation of the counter function .......................................................................................... .......... 222 8.8 operation of the square wave output initial setting function .......................................................... 225 8.9 operation of stopping and restarting the 8/16-bit timer/counter .................................................... 227 8.10 status of the 8/16-bit timer/counter in each mode ......................................................................... .. 228 8.11 notes on using the 8/16-bit timer/counter ................................................................................. ...... 229 chapter 9 16-bit timer/counter ......................................................................... 233 9.1 overview of the 16-bit timer/counter ....................................................................................... ......... 234 9.2 configuration of the 16-bit timer/counter .................................................................................. ....... 236 9.3 pin of the 16-bit timer/counter ........................................................................................... .............. 238 9.4 registers of the 16-bit timer/counter ...................................................................................... .......... 239 9.4.1 timer control register (tmcr) ............................................................................................ ........ 240 9.4.2 16-bit timer count register (tcr) ........................................................................................ ....... 242 9.5 16-bit timer/counter interrupts ............................................................................................ .............. 243
xii 9.6 operation of the interval timer function ................................................................................... ....... 244 9.7 operation of the counter function .......................................................................................... .......... 246 9.8 status of the 16-bit timer/counter in each mode ............................................................................ . 248 9.9 notes on using the 16-bit timer/counter .................................................................................... ..... 249 9.10 programe example of the 16-bit timer/counter .............................................................................. . 250 chapter 10 external interrupts (edges) ....................................................... 255 10.1 overview of the external interrupt circuit ................................................................................ ......... 256 10.2 configuration of the external interrupt circuit ........................................................................... ........ 257 10.3 pins of the external interrupt circuit .................................................................................... ............. 258 10.4 registers of the external interrupt circuit ............................................................................... .......... 260 10.4.1 external interrupt control register (eic1 to eic2) ...................................................................... 261 10.5 external interrupt circuit interrupts ..................................................................................... .............. 263 10.6 operation of the external interrupt circuit ............................................................................... ......... 264 chapter 11 a/d converter ..................................................................................... 265 11.1 overview of the a/d converter ............................................................................................. ............ 266 11.2 configuration of the a/d converter ........................................................................................ ........... 267 11.3 pins of the a/d converter ................................................................................................. ................ 270 11.4 registers of the a/d converter ............................................................................................ ............. 273 11.4.1 a/d control register 1 (adc1) ........................................................................................... ......... 274 11.4.2 a/d control register 2 (adc2) ........................................................................................... ......... 276 11.4.3 a/d data registers (addh, addl) ......................................................................................... .... 278 11.4.4 a/d enable registers 1 to 2 (aden 1 to 2) ............................................................................... .. 279 11.5 a/d converter interrupt ................................................................................................... .................. 281 11.6 operation of the a/d converter ............................................................................................ ............ 282 11.7 notes on using the a/d converter .......................................................................................... .......... 284 11.8 program example of the a/d converter ...................................................................................... ..... 286 chapter 12 d/a converter ..................................................................................... 289 12.1 overview of the d/a converter ............................................................................................. ............ 290 12.2 configuration of the d/a converter ........................................................................................ ........... 291 12.3 pins of the d/a converter ................................................................................................. ................ 292 12.4 registers of the d/a converter ............................................................................................ ............. 293 12.4.1 d/a control register .................................................................................................... ................ 294 12.4.2 d/a data registers 1 and 2 (dadr1, 2) ................................................................................... ... 295 12.5 operation of the d/a converter ............................................................................................ ............ 296 chapter 13 comparator ........................................................................................ 297 13.1 overview of the comparator ................................................................................................ ............. 298 13.2 configuration of the comparator ........................................................................................... ............ 299 13.3 pins of the comparator .................................................................................................... ................. 303 13.4 registers of the comparator ............................................................................................... .............. 306 13.4.1 comparator control register 1 (cocr1) ................................................................................... . 308 13.4.2 comparator control register 2 (cocr2) ................................................................................... . 310 13.4.3 comparator status register 1 (cosr1) .................................................................................... .. 312 13.4.4 comparator interrupt control register 1 (cicr1) ....................................................................... 3 15 13.4.5 comparator status register 2 (cosr2) .................................................................................... .. 317
xiii 13.4.6 comparator interrupt control register (cicr2) ........................................................................... 319 13.4.7 comparator status register 3 (cosr3) .................................................................................... .. 321 13.4.8 comparator status register 4 (cosr4) .................................................................................... .. 323 13.4.9 comparator input allow register (cier) .................................................................................. .... 325 13.5 comparator interrupts ..................................................................................................... ................... 327 13.6 operation of the parallel discharge control ............................................................................... ....... 329 13.7 operation of the sequential discharge control ............................................................................. .... 330 13.8 sample application ........................................................................................................ .................... 331 chapter 14 uart/sio .................................................................................................. 333 14.1 overview of the uart/sio ................................................................................................ .............. 334 14.2 configuration of the uart/sio ............................................................................................ ............ 335 14.3 pins of the uart/sio ...................................................................................................... .................. 337 14.4 registers of the uart/sio ................................................................................................. ............... 339 14.4.1 serial mode control register 1 (smc1) ................................................................................... .... 340 14.4.2 serial mode control register 2 (smc2) ................................................................................... .... 342 14.4.3 baud rate generator reload register (src) .............................................................................. 344 14.4.4 serial status and data register (ssd) ................................................................................... ..... 345 14.4.5 serial input data register (sidr) ....................................................................................... ......... 347 14.4.6 serial output data register (sodr) ...................................................................................... ...... 348 14.5 uart/sio interrupt ....................................................................................................... ................... 349 14.6 operation of the uart/sio ................................................................................................ .............. 350 14.7 operation of the operation mode 0 ......................................................................................... .......... 351 14.8 operation of the operation mode 1 ......................................................................................... .......... 356 chapter 15 i 2 c .............................................................................................................. 363 15.1 overview of the i 2 c ........................................................................................................................... 3 64 15.2 configuration of the i 2 c ..................................................................................................................... 366 15.3 pins of the i 2 c ............................................................................................................................. ...... 370 15.4 registers of the i 2 c ........................................................................................................................... 3 72 15.4.1 i 2 c bus status register (ibsr) .................................................................................................. .. 374 15.4.2 i 2 c bus control register (ibcr) ................................................................................................. . 376 15.4.3 i 2 c clock control register (iccr) ............................................................................................... 379 15.4.4 i 2 c address register (iadr) ..................................................................................................... ... 381 15.4.5 i 2 c data register (idar) ........................................................................................................ ..... 382 15.4.6 i 2 c timeout control register (itcr) ............................................................................................ 383 15.4.7 i 2 c timeout status register (itsr) ............................................................................................. 385 15.4.8 i 2 c timeout data register (itod) ............................................................................................... 387 15.4.9 i 2 c timeout clock register (itoc) .............................................................................................. 388 15.4.10 i 2 c master timeout register (imto) ............................................................................................ 3 89 15.4.11 i 2 c slave timeout register (isto) .............................................................................................. 390 15.5 i 2 c interrupts .................................................................................................................. .................. 391 15.6 operation of the i 2 c ........................................................................................................................... 3 92 15.7 notes on using the i 2 c ...................................................................................................................... 395 15.8 operation of the timeout detection function ............................................................................... ..... 396 chapter 16 multi-address i 2 c ............................................................................... 401 16.1 overview of the multi-address i 2 c ..................................................................................................... 402
xiv 16.2 configuration of the multi-address i 2 c .............................................................................................. 404 16.3 pins of the multi-address i 2 c ............................................................................................................ 408 16.4 registers of the multi-address i 2 c .................................................................................................... 410 16.4.1 multi-address i 2 c bus status register (mbsr) ........................................................................... 412 16.4.2 multi-address i 2 c bus control register (mbcr) ......................................................................... 414 16.4.3 multi-address i 2 c clock control register (mccr) ...................................................................... 417 16.4.4 multi-address i 2 c address registers (madr1 to 6) .................................................................... 419 16.4.5 multi-address i 2 c data register (mdar) .................................................................................... 420 16.4.6 multi-address i 2 c timeout control register (mtcr) .................................................................. 421 16.4.7 multi-address i 2 c timeout status register (mtsr) .................................................................... 423 16.4.8 multi-address i 2 c timeout data register (mtod) ...................................................................... 425 16.4.9 multi-address i 2 c timeout clock register (mtoc) ..................................................................... 426 16.4.10 multi-address i 2 c master timeout register (mmto) .................................................................. 427 16.4.11 multi-address i 2 c slave timeout register (msto) ..................................................................... 428 16.4.12 multi-address i 2 c alert register (malr) ................................................................................. 429 16.5 multi-address i 2 c interrupts .............................................................................................................. 430 16.6 operation of the multi-address i 2 c ................................................................................................... 432 16.7 notes on using the multi-address i 2 c ............................................................................................... 435 16.8 operation of the timeout detection function ............................................................................... .... 436 chapter 17 bridge circuit ..................................................................................... 441 17.1 overview of the bridge circuit ............................................................................................ .............. 442 17.2 configuration of the bridge circuit ....................................................................................... ............. 443 17.3 pins of the bridge circuit ................................................................................................ .................. 444 17.4 registers of the bridge circuit ........................................................................................... ............... 447 17.4.1 bridge circuit selection register 1 ( brsr1) ............................................................................ .. 448 17.4.2 bridge circuit selection register 2 (brsr2) ............................................................................. .. 450 17.4.3 bridge circuit selection register 3 (brsr3) ............................................................................. .. 452 chapter 18 lcd controller driver ................................................................... 455 18.1 overview of the lcd controller driver ..................................................................................... ......... 456 18.2 configuration of the lcd controller driver ................................................................................ ....... 457 18.2.1 internal dividing resistors of the lcd controller driver .............................................................. 4 59 18.2.2 external dividing resistor of lcd controller driver .................................................................... 461 18.3 pins of the lcd controller driver ......................................................................................... ............. 463 18.4 registers of the lcd controller driver .................................................................................... ......... 465 18.4.1 lcdc control register 1 (lcr1) .......................................................................................... ....... 466 18.4.2 lcdc control register 2 (lcr2) .......................................................................................... ....... 469 18.4.3 lcdc control register 3 (lcr3) .......................................................................................... ....... 471 18.4.4 lcdc control register 4 (lcr4) .......................................................................................... ....... 473 18.5 lcd display ram in the lcd controller driver .............................................................................. .. 475 18.6 operation of the lcd controller driver .................................................................................... ......... 477 18.6.1 output waveforms during lcd controller driver operation (1/2 duty) ....................................... 479 18.6.2 output waveforms during lcd controller driver operation (1/3 duty) ...................................... 482 18.6.3 output waveforms during lcd controller driver operation (1/4 duty) ...................................... 485 chapter 19 wild register function ................................................................. 489 19.1 overview of the wild register function .................................................................................... ........ 490
xv 19.2 configuration of the wild register function ............................................................................... ....... 491 19.3 registers of the wild register function ................................................................................... ......... 493 19.3.1 data setting registers (wrdr0 to 5) ..................................................................................... ..... 494 19.3.2 upper address setting registers (wrarh0 to 5) ....................................................................... 496 19.3.3 lower address setting registers (wrarl 0 to 5) ....................................................................... 49 8 19.3.4 address comparison enable register (wren) ........................................................................... 500 19.4 operation of the wild register function ................................................................................... ......... 502 appendix ...................................................................................................................... .... 503 appendix a i/o maps ......................................................................................................... ................... 504 appendix b overview of instructions ............................................................................................ ............ 510 b.1 overview of f 2 mc-8l instructions .................................................................................................. 511 b.2 addressing ................................................................................................................. ..................... 514 b.3 special instructions ....................................................................................................... .................. 518 b.4 bit manipulation instructions (setb, clrb) ................................................................................. .. 521 b.5 f 2 mc-8l instructions ............................................................................................................ .......... 522 b.6 instruction map ............................................................................................................ .................... 528 appendix c mask options ........................................................................................................ ................ 529 appendix d one-time prom and eprom microcontroller write specification ....................................... 530 appendix e pin statuses of the mb89570 series .................................................................................. .. 531 index .......................................................................................................................... .........533
xvi
1 chapter 1 overview this chapter describes the features and basic specifications of the mb89570 series. 1.1 "mb89570 series features" 1.2 "product lineup in the mb89570 series" 1.3 "differences of various product and precautions for selecting the products" 1.4 "block diagram of the mb89570 series" 1.5 "pin assignment" 1.6 "package dimensions" 1.7 "pin description" 1.8 "i/o circuit type"
2 chapter 1 overview 1.1 mb89570 series features the mb89570 series is a general-purpose single chip microcontroller that contains, in addition to a compact instruction set, such rich peripheral functions as the dual clock control, 5-stage operation speed control, sm bus compliant i 2 c bus interface, comparator for battery control, 10-bit a/d converter, lcd controller/driver, and external interrupts. n mb89570 series features m package ? lqfp package (0.5 mm pitch) ? tqfp package (0.4 mm pitch) m high-speed operation at low voltage ? minimum instruction execution time: 0.4 m s (for oscillator frequency 10 mhz) m f 2 mc-8l cpu core instruction set appropriate to the controller ? multiplication/division instruction ? 16-bit operation ? branch instruction by the bit test ? bit operation instructions, etc. m dual clock control ? main clock: up to 10 mhz (4 clock operating speeds can be set. oscillation stops in subclock mode) ? subclock: 32.768 khz (operating clock in subclock mode) m dual timer operation ? 21-bit timebase timer ? watch prescaler (17 bits) m uart/serial interface ? uart/sio can be switched. m i 2 c ? sm bus compliant ? timeout can be detected.
3 1.1 mb89570 series features m multi-address i 2 c ? sm bus compliant ? timeout can be detected. ? 6 addresses support ? alert function support m bridge circuit ? three bus connection routes can be switched by the i 2 c/multi-address i 2 c (uart) m external interrupt ? external interrupt (4 x edge detection): four inputs are independent and can be used for release from low-power mode (the rising edge, falling edge, and both edges can be selected for edge detection) m comparator function ? a selecting circuit for battery control is contained. ? a comparator capable of changing the hysteresis width is contained. m 10-bit a/d converter ? 12 channels of a/d converters with the 10-bit resolution are contained. m 8-bit d/a converter ? 8-bit d/a converter x 2 channels m 16-bit timer counter ? usable as an event counter m 8/16-bit timer/counter ? usable as 8-bit timer x 2 channels or 16-bit timer x 1 channel m lcd controller/driver ? 14seg x 4com (up to 56 pixels) ? exclusively for segment output: 8 ? for both of general purpose and lcd segment: 6 m low-power consumption (standby mode) ? stop mode (almost no power consumption for stopping oscillation) ? sleep mode (about 1/3 of the normal power consumption to stop cpu) ? watch mode (power consumption to stop operations other than the watch prescaler is very low) ? sub-mode
4 chapter 1 overview m up to 82 i/o ports ? general purpose i/o port (n channel open-drain): 28 ? general purpose i/o port (cmos): 49 ? general purpose input port (cmos): 1 ? general purpose output port (n channel open drain): 4
5 1.2 product lineup in the mb89570 series 1.2 product lineup in the mb89570 series 12 products are available in the mb89570 series. table 1.2-1 "mb89570 series product lineup" lists the products available and table 1.2-2 "mb89570 series cpu and peripheral functions" lists the cpu and peripheral functions. n product lineup in the mb89570 series n selection of the oscillation stabilization wait time in MB89577, it is possible to select the initial value of the oscillator stabilization wait time when the mask rom product is ordered. table 1.2-1 mb89570 series product lineup mb89pv570 (*1) mb89p579a MB89577 rom size - 60kb 32kb ram size 3kb 3kb 3kb package lqfp100 lqfp100 tqfp100 lqfp100 tqfp100 classifications evaluation product one time prom product mask product *1: in mb89pv570, only the evaluation function (function in which development tools can be used) is available. the piggyback function (function in which e 2 prom can be mounted) cannot be used. oscillation stabilization wait time selection remarks 2 14 /f ch 1.63 ms (if f=10mz) 2 17 /f ch 13.1 ms (if f=10mz) 2 18 /f ch 26.2 ms (if f=10mz)
6 chapter 1 overview table 1.2-2 mb89570 series cpu and peripheral functions item specifications cpu function number of basic instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, and 16-bit minimum instruction execution time: 0.4 m s (at 10 mhz) interrupt processing time: 3.6 m s (at 10 mhz) peripheral function port general purpose i/o port (n-ch open-drain): 28 general purpose i/o port (cmos): 49 general purpose input only port (cmos): 1 general purpose output only port (n-ch open-drain): 4 total: 82 (maximum) timebase timer 21-bit interrupt cycle for 10 mhz main clock (0.82 ms, 3.3 ms, 26.2 ms, 419.4 ms) watchdog timer reset generation cycle for 10 mhz of the main clock (minimum 209.7 ms) for 32. 768 khz of the sub clock (minimum 500 ms) sm bus compliant i 2 c bus support of the i 2 c bus of philips and the sm bus proposed by intel i 2 c bus (sm bus compliant) x 1 channel multi-address i 2 c bus (sm bus compliant) x 1 channel master/slave sending/receiving. slave general call address detection function. bus error function. arbitration function. transfer direction detection function. repeated generation and detection function of the start condition. timeout detection function. alert function (only for the multi-address i 2 c) uart/sio data can be transferred in uart/sio. variable data length (7/8 bits), baud rate generator contained, transfer rate (1200 to 78125 bps at 10 mhz), full duplex with double buffers, nrz transfer format, error detection function, and data transferable both in clock synchronous (sio) and clock asynchronous (uart) modes comparator a comparator that can change the hysteresis width is contained. the battery voltage, mounting/dismounting, and instantaneous interruption are detected, and the parallel and serial charging/discharging are controlled. the serial and parallel connection control is performed by software. a/d converter 10-bit x 12 channels d/a converter 8-bit x 2 channels 16-bit timer/counter 16-bit timer operation 16-bit event counter operation 8/16-bit timer/counter 8-bit timer x 2 channels (usable as 16-bit timer x 1 channel) lcd controller/driver up to 14seg x 4com (the lcd output/n-ch open-drain i/o port can be selected) external interrupt 4 (edges can be selected) standby mode sub-mode/sleep mode/watch mode/stop mode
7 1.3 differences of various product and precautions for selecting the products 1.3 differences of various product and precautions for selecting the products this section explains the differences among the models available in the mb89570 series and precautions when selecting various models. n differences of various product and precautions for selecting the products m correspondence table between the package and the product type m memory space before evaluating products using piggyback products, check the differences between the piggyback products and the products actually used. m consumption current ? when operating at a low speed, the power consumption of models with one-time prom or eprom is higher than that with mask rom. however, the power consumption in sleep/stop mode are comparable for both. ? for details on each package, see section 1.6 "package dimensions". ? for details on the power consumption, see the electric characteristics in "data sheet". ? operating voltage ? the operating voltage is dependent on the product type. ? for details, see "data sheet". m mask option the options that can be selected and the methods of specifying are dependent on respective products. before using the options, see appendix c "mask options". mb89pv570 mb89p579a MB89577 fpt-100p-m05 (lqf-100 0.5mm pitch) no yes yes ftp-100-m18 (tqfp-100 0.4 mm pitch) no yes yes mqp-100c-p02 (mqfp-100 0.5 mm pitch) yes no (*1) no (*1) *1: a pin pitch conversion socket (sun hayato) is available. 100sqf-100tqf-8l-fj: for mqp-100c-p02 --> fpt-100p-m18 conversion
8 chapter 1 overview 1.4 block diagram of the mb89570 series this section shows an overall block diagram of the mb89570 series. n block diagram of the mb89570 series figure 1.4-1 mb89570 series overall block diagram rstx reset circuit (wdt, power-on reset) n-ch open-drain i/o (ports 6, a, and b) vcc,vss,vss,moda,bvcc, avcc,avss,cvcc,cvss other pins cmos i/o (port 7) p84/ec p35/uo3 internal bus n-ch open-drain i/o (port 3) i c bus voltage compare x0 x1 main clock oscillator circuit clock control timebase timer r a m f 2 mc-8l c p u pb0/v0 pb3/v3 bridge circuit (multi address) p31/sda1 p32/alert cvrh2 16-bit timer lcd controller 2 cmos i/o port (port 8) pb4/com0 pb7/com3 pa0/seg00 pa7/seg07 p60/seg08 p63/seg11 cmos i/o (port 8) d/a converter p83/int3 p80/int0 avr p92/da2 p91/da1 p90/an3 external interrupt p17/an11 p10/an4 x0a x1a subclock oscillator circuit 4 4 2 8 6 4 p64/seg12/u02 p65/seg13/u01 2 4 8 4 r o m 8/16-bit timer cmos i/o port (ports 0 and 2) p20/to1 p21,p22, 6 p23/to2 watch prescaler i c bus 2 uart/sio 2 n-ch open-drain i/o (port 4) p30/scl1 p43/sda4/ui2 p42/scl4/uck2 p41/sda3/ui1 p40/scl3/uck1 p34/sda2/ui3 p33/scl2/uck3 p77/vsi3 p76/vol3 p75/vsi2 p74/vol2 p73/vsi1 p72/vol1 p71/dcin2 p70/dcin cvrl cvrh1 battery selecter p87/an2/sw3 p85/an0/sw1 p53/acq p52/ale3 p50/alr1 3 3 3 3 cmos i/o (port 5) cmos i/o (port 9) 2 4 a/d converter cmos i/o (port 1) 8 2 8 comparator p56/ofb3 p54/ofb1 3 3 4 p00 p07 8 p24 p27
9 1.5 pin assignment 1.5 pin assignment figure 1.5-1 "mb89570 series pin assignment" shows a pin assignment of the mb89570 series. n pin assignment of the mb89570 series (fpt-100p-m05, fpt-100p-m18, mqp-100c-p02) figure 1.5-1 mb89570 series pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 moda x0 x1 rstx v ss p20/to1 p21 p22 p23/to2 p24 p25 p26 p27 p30/scl1 p31/sda1 p32/alert p33/scl2/uck3 p34/sda2/ui3 p35/uo3 p40/scl3/uck1 p41/sda3/ui1 p42/scl4/uck2 p43/sda4/ui2 bv cc p50/alr1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p86/an1/sw2 p85/an0/sw1 av ss p84/ec p83/int3 p82/int2 p81/int1 p80/int0 cvrh2 cvrh1 cvrl p77/vsi3 p76/vol3 p75/vsi2 p74/vol2 p73/vsi1 p72/vol1 p71/dcin2 p70/dcin cv ss cv cc p65/seg13/u01 p64/seg12/u02 p63/seg11 p62/seg10 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 x0a x1a v cc p07 p06 p05 p04 p03 p02 p01 p00 avr p17/an11 p16/an10 p15/an9 p14/an8 p13/an7 p12/an6 p11/an5 p10/an4 av cc p92/da2 p91/da1 p90/an3 p87/an2/sw3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p51/alr2 p52/alr3 p53/aco p54/ofb1 p55/ofb2 p56/ofb3 pb0/v0 pb1/v1 pb2/v2 pb3/v3 pb4/com0 pb5/com1 pb6/com2 pb7/com3 pa0/seg00 pa1/seg01 pa2/seg02 pa3/seg03 pa4/seg04 pa5/seg05 pa6/seg06 v cc pa7/seg07 p60/seg08 p61/seg09 (top view)
10 chapter 1 overview 1.6 package dimensions three types of packages are available in the mb89570 series. n package dimensions of fpt-100p-m05 eiaj code : p-lfqfp100-14 14-0.50 100-pin plastic lqfp lead pitch 0.50 mm package width package length 14.0 14.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.65g 100-pin plastic lqfp (fpt-100p-m05) (fpt-100p-m05) c 2000 fujitsu limited f100007s-3c-5 14.000.10(.551.004)sq 16.000.20(.630.008)sq 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.0057.0022) 0.08(.003) "a" index .059 +.008 +0.20 1.50 (mounting height) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) details of "a" part (stand off) dimensions in mm (inches). pins width and pins thickness include plating thickness.
11 1.6 package dimensions n package dimensions of fpt-100p-m18 100-pin plastic tqfp lead pitch 0.40 mm package width package length 12 12 mm lead shape gullwing sealing method plastic mold length of flat portion of pins 1.20 mm max 100-pin plastic tqfp (fpt-100p-m18) (fpt-100p-m18) 1997 fujitsu limited f100029s-1c-1 details of "a" part c 0.45/0.75 (.018/.0295) 0.25(.010) 0.100.05(.004.002) (stand off height) 1.20(.047)max mounting height 1 12.000.10(.472.004)sq 14.000.20(.551.008)sq 0.40(.016) typ 0.07(.003) m 0.08(.003) "a" .006 +.002 +0.05 0.145 25 0.180.035 (.007.001) 50 26 75 51 100 76 index dimensions in mm (inches).
12 chapter 1 overview n package dimensions of mqp-100c-p02 100-pin ceramic mqfp lead pitch 0.50 mm lead shape straight motherboard material ceramic mounted package material plastic 100-pin ceramic mqfp (mqp-100c-p02) (mqp-100c-p02) c 1994 fujitsu limited m100002sc-2-2 14.820.35 (.583.014) 15.000.25 (.591.010) pin no.1 index 1.020.13 (.040.005) 7.14(.281) typ pad no.1 index 0.150.05 (.006.002) 9.94(.392)max 1.10 +0.45 +.018 .043 10.92(.430) typ 4.50(.177)sq typ 12.00(.472)typ 17.20(.667)typ 12.00(.472) typ 17.20(.667) typ 0.180.05 (.007.002) 0.500.15 (.0197.0060) 0.30(.012) typ 10.92(.430) typ sq sq dimensions in mm (inches).
13 1.7 pin description 1.7 pin description table 1.7-1 "pin description" provide pin function explanations. alphabets in the i/o circuit field of table 1.7-1 "pin description" correspond to those in the classification field of table 1.8-1 "i/o circuit type". n pin description table 1.7-1 pin description pin no. pin name i/o circuit type function 1 moda a pin to specify the operation mode 2x0 c pin for crystal oscillator (max 10 mhz) 3x1 4 rstx d reset i/o pin 5 vss C power pin (gnd) 6p20/t01 b general-purpose i/o port. this pin is used also for 8/16-bit timer output. 7p21 general-purpose i/o port 8p22 9p23/t02 general-purpose i/o port. this pin is used also for 8/16-bit timer output. 10 p24 general-purpose i/o port 11 p25 12 p26 13 p27 14 p30/scl1 f general-purpose n-ch open-drain i/o port. this pin is also used for scl1 i/o of the multi-address i 2 c. 15 p31/sda1 general-purpose n-ch open-drain i/o port. this pin is also used for sda1 i/o of the multi-address i 2 c. 16 p32/alert h general-purpose n-ch open-drain i/o port. this pin is also used for alert i/o of the multi-address i 2 c.
14 chapter 1 overview 17 p33/scl2/uck3 g general-purpose n-ch open-drain i/o port. this pin is also used for scl2 i/o of i 2 c and uck3 i/o of uart. 18 p34/sda2/ui3 general-purpose n-ch open-drain i/o port. this pin is also used for sda2 i/o of i 2 c and ui3 input of uart. 19 p35/u03 h general-purpose n-ch open-drain i/o port. this pin is also used for uo3 output of uart. 20 p40/scl3/uck1 g general-purpose n-ch open-drain i/o port. this pin is also used for scl/uck1 i/o of a bridge circuit. 21 p41/sda3/ui1 general-purpose n-ch open-drain i/o port. this pin is also used for sda3/ui1 i/o of a bridge circuit. 22 p42/scl4/uck2 general-purpose n-ch open-drain i/o port. this pin is also used for scl4/uck2 i/o of a bridge circuit. 23 p43/sda4/ui2 general-purpose n-ch open-drain i/o port. this pin is also used for sda4/ui2 i/o of a bridge circuit. 24 bvcc C power pin of a bridge circuit 25 p50/alr1 b general-purpose i/o port. this pin is also used for alarm signal output when battery 1 runs down. 26 p51/alr2 general-purpose i/o port. this pin is also used for alarm signal output when battery 2 runs down. 27 p52/alr3 general-purpose i/o port. this pin is also used for alarm signal output when battery 3 runs down. 28 p53/ac0 b general-purpose i/o port. this pin is also used for ac power set signal output. 29 p54/ofb1 b general-purpose i/o port. this pin is also used for battery 1 discharge control signal output of the comparator. 30 p55/ofb2 general-purpose i/o port. this pin is also used for battery 2 discharge control signal output of the comparator. 31 p56/ofb3 general-purpose i/o port. this pin is also used for battery 3 discharge control signal output of the comparator. table 1.7-1 pin description (continued) pin no. pin name i/o circuit type function
15 1.7 pin description 32 pb0/v0 i n-ch open-drain i/o pin this pin is also used by the lcd driving power pin. 33 pb1/v1 34 pb2/v2 35 pb3/v3 36 pb4/com0 j n-ch open-drain i/o pin this pin is also used by the lcd controller common output dedicated pin. 37 pb5/com1 38 pb6/com2 39 pb7/com3 40 pa0/seg00 j n-ch open-drain i/o pin this pin is also used by the lcd controller segment output dedicated pin. 41 pa1/seg01 42 pa2/seg02 43 pa3/seg03 44 pa4/seg04 45 pa5/seg05 46 pa6/seg06 47 vcc C power supply pin 48 pa7/seg07 j n-ch open-drain i/o pin this pin is also used by the lcd controller segment output dedicated pin. 49 pa60/seg08 j n-ch open-drain i/o pin this pin is also used by the lcd controller segment output pin. 50 pa61/seg09 51 pa62/seg10 52 pa63/seg11 53 pa64/seg12/ uo2 n-ch open-drain i/o pin this pin is also used by the lcd controller segment output pin/uart u0 pin. 54 pa65/seg13/ uo1 55 cvcc C comparator power supply pin 56 cvss C power supply pin (gnd) 57 p70/dcin n general-purpose i/o port. this pin is also used for ac power monitoring input of the comparator. 58 p71/dcin2 59 p72/vol1 general-purpose i/o port. this pin is also used for battery 1 power instantaneous interruption monitoring input of the comparator. table 1.7-1 pin description (continued) pin no. pin name i/o circuit type function
16 chapter 1 overview 60 p73/vs11 n general-purpose i/o port this pin is also used for battery 1 indicator monitoring input of the comparator. 61 p74/vol2 general-purpose i/o port this pin is also used for battery 2 power instantaneous interruption monitoring input of the comparator. 62 p75/vsi2 general-purpose i/o port this pin is also used for battery 2 indicator monitoring input of the comparator. 63 p76/vol3 general-purpose i/o port this pin is also used for battery 3 power instantaneous interruption monitoring input of the comparator. 64 p77/vsi3 general-purpose i/o port this pin is also used for battery 3 indicator monitoring input of the comparator. 65 cvrl C standard power input pin of the comparator 66 cvrh1 67 cvrh2 68 p80/int0 k general-purpose i/o port these pins are also used for external interrupts. when an external interrupt occurs, it is hysteresis input. 69 p81/int1 70 p82/int2 71 p83/int3 72 p84/ec o general-purpose input port this pin is also used by ec of the 16-bit timer and 8/16-bit timer. 73 avss C power (gnd) pin 74 p85/an0/sw1 l general-purpose i/o port this pin is also used for analog input/comparator input. 75 p86/an1/sw2 76 p87/an2/sw3 77 p90/an3 e general-purpose i/o port this pin is also used for analog input. 78 p91/da1 m general-purpose i/o port this pin is also used for d/a converter output. 79 p92/da2 80 avcc C power supply pin of the a/d and d/a converters table 1.7-1 pin description (continued) pin no. pin name i/o circuit type function
17 1.7 pin description 81 p10/an4 e general-purpose i/o port this pin is also used for analog input. 82 p11/an5 83 p12/an6 84 p13an7 85 p14/an8 86 p15/an9 87 p16/an10 88 p17/an11 89 avr C reference input pin of the a/d converter 90 p00 b general-purpose i/o port 91 p01 92 p02 93 p03 94 p04 95 p05 96 p06 97 p07 98 vcc C power supply pin 99 x1a c crystal oscillator pin (sub clock) 100 x0a table 1.7-1 pin description (continued) pin no. pin name i/o circuit type function
18 chapter 1 overview 1.8 i/o circuit type table 1.8-1 "i/o circuit type" list the i/o circuit forms. alphabets in the classification field of table 1.8-1 "i/o circuit type" correspond to those in the i/o circuit form field of table 1.7-1 "pin description". n i/o circuit type table 1.8-1 i/o circuit type classification circuit remarks a ? cmos input b ?cmos i/o c ? oscillation feedback resistor main clock : approximately 1 m w sub clock : approximately 4.5 m w d ? reset input/output pin ? output pull-up resistor (p- ch): approximately 50 k w ? hysteresis input p-ch n-ch n-ch n-ch n-ch x1(x1a) x0(x0a) p-ch p-ch p-ch n-ch r input
19 1.8 i/o circuit type e ?cmos i/o ? analog input f ? n-ch open-drain output ?cmos i/o ?i 2 c input g ? n-ch open-drain output ?cmos i/o ?i 2 c input ? uart input h ? n-ch open-drain i/o i ? n-ch open-drain i/o ? lcd built-in divided resistance input table 1.8-1 i/o circuit type (continued) classification circuit remarks p-ch n-ch port input analog input port input n-ch i c input 2 port input i c input n-ch 2 uart input n-ch port input n-ch lcd built-in divide d resistance input
20 chapter 1 overview j ? cmos input ? lcd output ? n-ch open-drain i/o k ? cmos input ? hysteresis input (during the input of an external interrupt) l ?cmos i/o ? analog input ? comparator input m ?cmos i/o ? d/a converter output table 1.8-1 i/o circuit type (continued) classification circuit remarks n-ch port input p-ch n-ch port input external interrupt input port input p-ch n-ch analog input comparator input + - port input d/a output d/a output en p-ch n-ch
21 1.8 i/o circuit type n ?cmos i/o ? comparator input o ? cmos input table 1.8-1 i/o circuit type (continued) classification circuit remarks port input p-ch n-ch comparator input + - input
22 chapter 1 overview
23 chapter 2 handling device this chapter describes the precautions to be taken when using the mb89570 series. 2.1 "notes on handling devices"
24 chapter 2 handling device 2.1 notes on handling devices this section describes the precautions to be taken when handling the power supply voltage and pins of the device. n notes on handling devices m preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins, or if voltage higher than ratings is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc , bv cc , cv cc , avr, cvrh1, cvrh2, and cvrl) and analog input from exceeding the digital power supply (v cc) when the analog system power supply is turned on and off. m treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull- up or pull-down resistor. m treatment of power supply pins on microcontroller with a/d and d/a converters connect to be av cc = bv cc = cv cc = v cc and av ss = avr = cv ss = cvrl = cvrh1 = cvrh2 = v ss even if the a/d and d/a converters are not in use. m treatment of unused input pins be sure to leave (internally connected) n.c. pins open. m power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. m precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode.
25 chapter 3 cpu this chapter describes the functions and operations of the cpu. 3.1 "memory space" 3.2 "dedicated registers" 3.3 "general-purpose registers" 3.4 "interrupts" 3.5 "resets" 3.6 "external reset pin" 3.7 "clock" 3.8 "standby mode (low power consumption)" 3.9 "memory access mode"
26 chapter 3 cpu 3.1 memory space the memory space of the mb89570 series is 64 kbytes and is made up of the i/o area, ram area, rom area, and external area. some areas in the memory space, such as the general-purpose registers and vector table, are used for specific applications. n configuration of the memory space m i/o area (address: 0000 h - 007f h ) ? this area is allocated to the control registers and data registers of the built-in peripheral devices. ? since the i/o area is allocated to a part of the memory space, it can be accessed like normal memory. the area can be accessed faster using direct addressing. m ram area ? static ram is contained as a built-in data area. ? the internal ram size is dependent on the part number. ?80 h to ff h can be accessed faster using direct addressing (depending on the part number, the available area may be limited). ?100 h to 1ff h can be used as a general-purpose register area. ? if a reset occurs during a write operation to ram, data at the address to which data is being written cannot be guaranteed. m rom area ? rom is contained as an internal program area. ? the internal rom size is dependent on the part number. ? ffc0 h to ffff h are used as, for example, a vector table.
27 3.1 memory space n memory map figure 3.1-1 memory map vector table (reset/interrupt/vector call instructions) 0000 h 0080 h 0100 h 1000 h mb89pv570 i/o ram registers access prohibited external rom 0000 h 0080 h 0100 h 0200 h 8000 h ffff h MB89577 i/o ram registers rom ffff h access prohibited 0200 h ffc0 h ffc0 h 0000 h 0080 h 0100 h 0200 h 1000 h ffff h mb89p579a i/o ram registers eprom access prohibited ffc0 h 0c80 h 0c92 h wild registers 0c80 h 0c92 h wild registers 0c80 h 0c92 h wild registers
28 chapter 3 cpu 3.1.1 special areas in addition to the i/o area, the general-purpose register area and vector table area are available as areas for specific applications. n general-purpose register area (address: 0100 h - 01ff h ) ? this area is used for 8-bit arithmetic operations and transfer. supplementary registers are provided. ? since this area is allocated to a part of the ram area, it can also be used as normal ram. ? when this area is used as a general-purpose register, it can be accessed faster using shorter instructions by general-purpose register addressing. for details, see section 3.2.2 "register bank pointer (rp)" and section 3.3 "general-purpose register". n vector table area (address: ffc0 h - ffff h ) ? this area is used as vector tables of the vector call instructions, interrupts, and reset. ? this area is allocated to the highest ranges of the rom area, and the start address of the corresponding processing routine is set to the address of each vector table. table 3.1-1 "vector table" lists the addresses of the vector tables referenced corresponding to the vector call instructions, interrupts, and reset. for details, see section 3.4 "interrupts", section 3.5 "reset", and "(6) callv #vct" of appendix b.3 "special instructions". table 3.1-1 vector table vector call instruction vector table address high low callv #0 ffc0 h ffc1 h callv #1 ffc2 h ffc3 h callv #2 ffc4 h ffc5 h callv #3 ffc6 h ffc7 h callv #4 ffc8 h ffc9 h callv #5 ffca h ffcb h callv #6 ffcc h ffcd h callv #7 ffce h ffcf h
29 3.1 memory space table 3.1-1 vector table (continued) interrupt name vector table address high low irqf ffdc h ffdd h irqe ffde h ffdf h irqd ffe0 h ffe1 h irqc ffe2 h ffe3 h irqb ffe4 h ffe5 h irqa ffe6 h ffe7 h irq9 ffe8 h ffe9 h irq8 ffea h ffeb h irq7 ffec h ffed h irq6 ffee h ffef h irq5 fff0 h fff1 h irq4 fff2 h fff3 h irq3 fff4 h fff5 h irq2 fff6 h fff7 h irq1 fff8 h fff9 h irq0 fffa h fffb h mode data * fffd h reset vector fffe h ffff h *: fffc h is not available (set ff h )
30 chapter 3 cpu 3.1.2 storing 16-bit data in memory higher data of 16-bit data and stacks are stored in the areas of smaller address values on memory. n storage of 16-bit data on ram when writing 16-bit data into memory, the higher byte of the data is stored at the lower address. the lower byte of the data is stored at the next address. when reading memory, the same procedure is executed.figure 3.1-2 "storing 16-bit data in memory" shows the storing 16-bit data in memory. figure 3.1-2 storing 16-bit data in memory n storage of a 16-bit operand also when 16 bits are specified in an operand of an instruction, the higher byte is stored at the nearby operation code (instruction) and the lower byte is stored at the next address. this is the same if the operand points to a memory address or is 16-bit immediate data. figure 3.1-3 "16-bit data in instructions" shows the storing 16-bit data in instructions. figure 3.1-3 16-bit data in instructions before execution a 1 2 3 4 h memory 0080 h 0081 h 0082 h 0083 h after execution a 1 2 3 4 h memory 0080 h 0081 h 0082 h 0083 h 12 h 34 h movw 0081h, a [example] mov a, 5678h ;extended address movw a, #1234h ;16-bit immediate data after assembling x x x 0 h xx xx x x x 2 h 60 56 78 ;extended address x x x 5 h e4 12 34 ;16-bit immediate data x x x 8 h xx
31 3.1 memory space n storage of 16-bit data on the stack data of the 16-bit length register saved on the stack due, for example, to an interrupt, is also stored in the same manner, with the higher byte at the smaller address.
32 chapter 3 cpu 3.2 dedicated registers the dedicated registers in the cpu consist of the program counter (pc), two arithmetic operation registers (a and t), three address pointers (ix, ep, and sp), and the program status (ps). all registers are 16 bits. n dedicated register configuration the dedicated registers in the cpu consist of seven 16-bit registers. some of these registers are also able to be used as 8-bit registers, using the lower 8 bits only. figure 3.2-1 "dedicated register configuration" shows the structure of the dedicated registers. figure 3.2-1 dedicated register configuration n dedicated register functions m program counter (pc) the program counter is a 16-bit counter that indicates the memory address of the instruction currently being executed by the cpu. instruction execution, interrupts, resets, and similar update the contents of the program counter. the initial value during a reset is the read address of the mode data (fffd h ). m accumulator (a) the accumulator is a 16-bit arithmetic operation register. the accumulator is used to perform arithmetic operations and data transfers with data in memory or in other registers such as the temporary accumulator (t). the content of the accumulator can be treated as either word (16- bit) or byte (8-bit) data. only the lower 8 bits (al) of the accumulator are used for byte arithmetic operations or transfers. in this case, the upper 8 bits (ah) remain unchanged. the content of the accumulator after a reset is indeterminate. pc a t ix ep sp rp ccr 16 bits ps initial value indeterminate indeterminate indeterminate indeterminate indeterminate fffd h : program counter a register for indicating the current instruction storage positions : accumulator a temporary register for storing arithmetic operations or transfer instructions : temporary accumulator a register which performs arithmetic operations with the accumulator : index register a register for indicating an index address : extra pointer a pointer for indicating a memory address : stack pointer a register for indicating the current stack location : program status a register for storing a register bank pointer and condition code i-flag = "0", il0, il1 = "11" other bits are indeterminate
33 3.2 dedicated registers m temporary accumulator (t) the temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (a). the content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations. for byte-length arithmetic operations, only the lower 8 bits of the temporary accumulator (tl) are used and the upper 8 bits (th) are not used. executing a transfer instruction to transfer data to the accumulator (a) automatically transfer the previous content of the accumulator to the temporary accumulator. in this case also, a byte transfer leaves the upper 8 bits of the temporary accumulator (th) unchanged. the content of the temporary accumulator after a reset is indeterminate. m index register (ix) the index register is a 16-bit register used to hold the index address. the index register is used in conjunction with a single byte offset value (-128 to +127). adding the sign-extended offset value to the index address generates the memory address for data access. the content of the index register after a reset is indeterminate. m extra pointer (ep) the extra pointer is a 16-bit register used to hold a memory address for data access. the content of the extra pointer after a reset is indeterminate. m stack pointer (sp) the stack pointer is a 16-bit register used to hold the address referenced during operations such as interrupts, subroutine calls, and the stack save and restore instructions. the value of the stack pointer during program execution is the address of the most recently saved data on the stack. the content of the stack pointer after a reset is indeterminate. m program status (ps) the program status is a 16-bit control register. the upper 8 bits contain the register bank pointer (rp) which points to the address of the current general-purpose register bank. the lower 8 bits contain the condition code register (ccr) which contains flags indicating the current cpu status. the two 8-bit registers which form the program status cannot be accessed independently (the program status can only be accessed by the movw a,ps and movw ps,a instructions). refer to the "f 2 mc-8l programming manual" for details on using the dedicated registers
34 chapter 3 cpu 3.2.1 condition code register (ccr) the condition code register (ccr) located in the lower 8 bits of the program status (ps) consists of the c, v, z, n, and h bits indicating the results of arithmetic operations and the contents of transfer data, and the i, il1, and il0 bits for control whether or not the cpu accepts interrupt requests. n structure of condition code register (ccr) figure 3.2-2 structure of condition code register n arithmetic operation result bits m half-carry flag (h) set when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an arithmetic operation. cleared otherwise. as this flag is for the decimal adjustment instructions, do not use this flag in cases other than addition or subtraction. m negative flag (n) set if the most significant bit (msb) is set to 1 as a result of an arithmetic operation. cleared when the bit is set to 0. m zero flag (z) set when an arithmetic operation results in 0. cleared otherwise. m overflow flag (v) set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. m carry flag (c) set when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in case of a shift instruction. half-carry flag interrupt enable flag interrupt level bits negative flag zero flag overflow flag carry flag bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r4 r3 r2 r1 r0 h i il1 il0 n z v c ccr initial value x011xxxx b rp ccr ps x: indeterminate
35 3.2 dedicated registers figure 3.2-3 "change of carry flag by shift instruction" shows the change of the carry flag by a shift instruction. figure 3.2-3 change of carry flag by shift instruction note: the condition code register is part of the program status (ps) and cannot be accessed independently. reference: in practice, the flag bits are rarely fetched and used directly. instead, the bits are used indirectly by instructions such as branch instructions (such as bnz) or the decimal adjustment instructions (daa, das). the content of the flags after a reset is indeterminate. c bit 7 bit 0 bit 7 bit 0 ? left shift (rolc) ? right shift (rorc) c
36 chapter 3 cpu n interrupt acceptance control bit m interrupt enable flag (i) interrupt is enabled when this flag is set to "1" and the cpu accepts interrupt. interrupt is prohibited when this flag is set to "0" and the cpu does not accept interrupt. the initial value after a reset is "0". normal practice is to set the flag to "1" by the seti instruction and clear to "0" by the clri instruction. m interrupt level bits (il1, il0) these bits indicate the level of the interrupt currently being accepted by the cpu. the value is compared with the interrupt level setting registers (ilr1 to ilr3) which have a setting for each peripheral function interrupt request (irq0 to irqb). given that the interrupt enable flag is enabled (i = "1"), the cpu only performs interrupt processing for interrupt requests with an interrupt level value that is less than the value of these bits. table 3.2-1 "interrupt level" lists the interrupt level priorities. the initial value after a reset is "11". reference: the interrupt level bits (il1, il0) are normally "11" when the cpu is not processing an interrupt (during main program execution). see section 3.4 "interrupts" for details on interrupts. table 3.2-1 interrupt level il1 il0 interrupt level high-low 00 1 01 10 2 11 3 high low (no interrupt)
37 3.2 dedicated registers 3.2.2 register bank pointer (rp) the register bank pointer (rp) located in the upper 8 bits of the program status (ps) indicates the address of the general-purpose register bank currently in use. the rp is converted to form the actual address in general-purpose register addressing. n structure of register bank pointer (rp) figure 3.2-4 "structure of register bank pointer" shows the structure of the register bank pointer. figure 3.2-4 structure of register bank pointer the register bank pointer indicates the address of the register bank currently in use. figure 3.2- 5 "rule for conversion of actual addresses of general-purpose register area" shows the relationship between the pointer contents and the actual address is based on the conversion rule. figure 3.2-5 rule for conversion of actual addresses of general-purpose register area the register bank pointer points to the memory block (register bank) in the ram area that is used for general-purpose registers. a total of 32 register banks are available. a register bank is specified by setting a value between 0 and 31 in the upper 5 bits of the register bank pointer. each register bank contains 8-bit general-purpose registers. registers are specified by the lower 3 bits of the operation codes. using the register bank pointer, the addresses 0100 h to 01ff h can be used as the general- purpose register area. however, the available area is limited on some products if internal ram only is used. the initial value after a reset is indeterminate. note: the register bank pointer is part of the program status (ps) and cannot be accessed independently. r4 r3 r2 r1 r0 h i il1 il0 n z v c rp initial value xxxxxxxx b rp ccr ps x: indeterminate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 a15 a14 a13 a12 a10 a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 "0" "0" "0" "0" "0" "0" "0" "1" r4 r3 r2 r1 r0 b2 b1 b0 upper bits of rp lower operation codes generated addresses
38 chapter 3 cpu 3.3 general-purpose registers the general-purpose registers are a memory block made up of banks, with 8 x 8-bit registers per bank. the register bank pointer (rp) is used to specify the register bank. the function permits the use of up to 32 banks, but the number of banks that can actually be used depends on how much ram the device has. register banks are valid for interrupt processing, vector call processing, and subroutine calls. n structure of general-purpose registers ? the general-purpose registers are 8 bits and located in the register banks of the general- purpose register area (in ram). ? one bank contains eight registers (r0 to r7) and up to a total of 32 banks. however, the number of banks available for general-purpose registers is limited on some products if internal ram only is used. ? the register bank currently in use is specified by the register bank pointer (rp). the lower three bits of the operation code specify general-purpose register 0 (r0) to general-purpose register 7 (r7). figure 3.3-1 "register bank structure" shows the register bank structure. figure 3.3-1 register bank structure lower 3 bits of the operation code *: the top address of a register bank = 0100 h + 8 (upper 5 bits of rp) r0 r1 r2 r3 r4 r5 r6 r7 r0 r7 r0 r7 : : : : : 000 001 010 011 100 101 110 111 000 111 000 111 100 h * 108 h * 1ff h 1f8 h * : : : : : bank 0 (rp="00000--- b ") bank 1 (rp="00001--- b ") bank 31 (rp="11111--- b ") bank 2 to bank 30 ? ? ? ? ? ? ? ? 32 banks (ram area) the number of banks is limited on available ram size.
39 3.3 general-purpose registers see section 3.1.1 "special areas" for the general-purpose register area available for each product. n features of general-purpose registers general-purpose registers have the following features: ? ram can be accessed at high-speed using short instructions (general-purpose register addressing). ? registers are grouped in blocks in the form of register banks. this simplifies the process of saving register contents and dividing registers by function. dedicated register banks can be permanently assigned for each interrupt processing or vector call (callv #0 to #7) processing routine by general-purpose register. for example, register bank 4 interrupt 2. for example, a particular interrupt processing routine only uses a particular register bank which cannot be written to unintentionally by other routines. the interrupt processing routine only needs to specify its dedicated register bank at the start of the routine to effectively save the general-purpose registers in use prior to the interrupt. therefore, saving the general-purpose registers to the stack or other memory location is not necessary. this allows high-speed interrupt handling while maintaining simplicity. also, as an alternative to saving general-purpose registers in subroutine calls, register banks can be used to create reentrant programs (programs that do not use fixed addresses and can be entered more than once) usually made by the index register (ix). note: if an interrupt processing routine changes the register bank pointer (rp), ensure that the program does not also change the interrupt level bits in the condition code register (ccr: il1, il0) when specifying the register bank.
40 chapter 3 cpu 3.4 interrupts the mb89570 series has 16 interrupt request input corresponding to peripheral functions. an interrupt level can be set independently. if an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller. the cpu performs interrupt operation according to how the interrupt is accepted. the cpu wakes up from standby modes, and returns to the interrupt or normal operation. n interrupt requests from peripheral functions table 3.4-1 "interrupt request and interrupt vector" lists the interrupt requests corresponding to the peripheral functions. on acceptance of an interrupt, execution branches to the interrupt processing routine. the contents of interrupt the vector table address corresponding to the interrupt request specifies the branch destination address for the interrupt processing routine. an interrupt processing level can be for each interrupt request in the interrupt level setting registers (ilr1, ilr2, ilr3, ilr4). three levels are available. if an interrupt request with the same or lower level occurs during execution of an interrupt processing routine, the letter interrupt is not normally processed until the current interrupt processing routine completes. if interrupt request set the same level occur simultaneously, the highest priority is irq0.
41 3.4 interrupts table 3.4-1 interrupt requests and interrupt vectors interrupt request vector table address bit name of the interrupt level setting register priority if interrupt requests with the same level occur simultaneously higher lower irq0 (external interrupt1) fffa h fffb h l01, l00 irq1 (external interrupt2) fff8 h fff9 h l11, l10 irq2 (unused) fff6 h fff7 h l21, l20 irq3 (a/d converter) fff4 h fff5 h l31, l30 irq4 (converter1) fff2 h fff3 h l41, l40 irq5 (converter2) fff0 h fff1 h l51, l50 irq6 (uart/sio) ffee h ffef h l61, l60 irq7 (timebase timer) ffec h ffed h l71, l70 irq8 (watch prescaler) ffea h ffeb h l81, l80 irq9 (i 2 c) ffe8 h ffe9 h l91, l90 irqa (i 2 c timeout) ffe6 h ffe7 h la1, la0 irqb (multi-address i 2 c) ffe4 h ffe5 h lb1, lb0 irqc (multi-address i 2 c timeout) ffe2 h ffe3 h lc1, lc0 irqd (16-bit timer/counter) ffe0 h ffe1 h ld1, ld0 irqe (8/16-bit timer) ffde h ffdf h le1, le0 irqf (unused) ffdc h ffdd h lf1, lf0 high low
42 chapter 3 cpu 3.4.1 interrupt level setting registers (ilr1, ilr2, ilr3, ilr4) the interrupt level setting registers (ilr1, ilr2, ilr3, ilr4) together contain 16 blocks of 2-bit data, with each data corresponding to an interrupt request from a peripheral function. the interrupt level for each interrupt is set in that interruptis corresponding 2-bit data (interrupt level setting bits). n structure of interrupt level setting registers (ilr1, ilr2, ilr3, ilr4) figure 3.4-1 structure of the interrupt level setting register two bits of the interrupt level setting registers are allocated to each interrupt request. the value of the interrupt level setting bits in these registers sets the interrupt priority (interrupt levels 1 to 3). the interrupt level setting bits are compared with the interrupt level bits in the condition code register (ccr: il1, il0). the cpu does not accept interrupt requests set to interrupt level 3. table 3.4-2 "interrupt level setting bit and interrupt level" shows the relationship between the interrupt level setting bits and the interrupt levels. l31 l21 l20 l11 l10 l01 l00 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 b h address 11111111 b initial value l30 register ilr1 l71 l61 l60 l51 l50 l41 l40 0 0 7 c h 11111111 b l70 ilr2 lb1 la1 la0 l91 l90 l81 l80 0 0 7 d h 11111111 b lb0 ilr3 w: write only w ww ww w w w w ww ww w w w w ww ww w w w lf1 le1 le0 ld1 ld0 lc1 lc0 0 0 7 e h 11111111 b lf0 ilr4 w ww ww w w w table 3.4-2 interrupt level setting bits and the interrupt level l01 to lf1 l00 to lf0 request interrupt level high-low 00 1 01 10 2 11 3 high low (no interrupt)
43 3.4 interrupts reference: the interrupt level bits in the condition code register (ccr: il1, il0) are normally "11" during main program execution. note: as the irl1, ilr2, and ilr3 registers are write-only, the bit manipulation instructions cannot be used.
44 chapter 3 cpu 3.4.2 interrupt processing the interrupt controller transmits the interrupt level to the cpu when an interrupt request is generated by a peripheral function. if the cpu is able to receive the interrupt, the cpu temporarily halts the currently executing program and executes the interrupt processing routine. n interrupt processing the procedure for interrupt operation is performed in the following order: interrupt source generated at peripheral function, set the interrupt request flag bit (request ff), discriminate the interrupt request enable bit (enable ff), the interrupt level (ilr1, ilr2, ilr3, ilr4 and ccr: il1, il0), simultaneously generated interrupt requests with the same level, then check the interrupt enable flag (ccr: i). figure 3.4-2 "interrupt processing" shows the interrupt processing. figure 3.4-2 interrupt processing start initialize peripheral is an interrupt request present at the peripheral? is interrupt request output enabled for the peripheral? check the interrupt priority level and transfer the level to the cpu compare the level with the il bits in ps is the level higher than il? i-flag = 1? interrupt processing routine clear interrupt request execute interrupt processing reti restore pc and ps save pc and ps to the stack pc ? interrupt vector update il in ps register file ipla internal data bus ir ps i il condition code register (ccr) check comparator wake-up from f 2 mc-8lcpu ram (5) (7) (6) (3) (4) enable ff request ff and peripherals level comparator interrupt controller (1) (3) (4) (5) (7) (6) yes yes yes yes no no no no stop mode wake-up from sleep mode main program execution (2) exit watch mode
45 3.4 interrupts note: as the interrupt request flag bit of a peripheral function is not cleared automatically when an interrupt request is received, the bit must be cleared by the program (normally, by writing "0" to the interrupt request flag bit) at interrupt processing routine. an interrupt wakes up the cpu from standby mode (low-power consumption). see section 3.8 "standby modes (low-power consumption)" for details. reference: if the interrupt request flag bit is cleared at the top of the interrupt processing routine, the peripheral function that has generated the interrupt becomes able to generate another interrupt during execution of the interrupt processing routine (resetting the interrupt request flag bit). however, the interrupts are not normally accepted until the current processing routine completes. (1) after a reset, all interrupt requests are disabled. initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ilr1, ilr2, ilr3, ilr4), and start peripheral function. the interrupt level can be set to 1, 2 or 3. level 1 is the highest priority, followed by level 2. setting level 3 disables the interrupt for that peripheral function. (2) execute the main program (for multiple interrupts, execute the interrupt processing routine). (3) the interrupt request flag bit (request ff) for a peripheral function is set to "1" when the peripheral function generates an interrupt source. if the interrupt request enable bit for the peripheral function is set to "enable" (enable ff = "1"), the peripheral function outputs the interrupt request to the interrupt controller. (4) the interrupt controller continuously monitors for interrupt requests from the peripheral functions and passes the interrupt level of the current interrupt request with the highest interrupt level to the cpu. the interrupt controller also evaluates the priority order if requests with the same level are present simultaneously. (5) if the interrupt level received by the cpu has a higher priority (a lower level value) than the level set in the interrupt level bits in the condition code register (ccr: il1, il0), the cpu checks the interrupt enable flag (ccr: i) and receives the interrupt if interrupts are enabled (ccr: i = "1"). (6) the cpu saves the contents of the program counter (pc) and program status (ps) on the stack, reads the top address of the interrupt processing routine from the interrupt vector table for the interrupt, updates the interrupt level bits in the condition code register (ccr: il1, il0) with the received interrupt level, and starts execution of the interrupt processing routine. (7) finally, on execution of the reti instruction, the cpu restores the program counter (pc) and program status (ps) values saved on the stack and resumes execution from the instruction following the last instruction executed before the interrupt.
46 chapter 3 cpu 3.4.3 multiple interrupts multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register for two or more interrupt requests from peripheral functions. n multiple interrupts if the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the cpu halts the current interrupt process and switches to accept the interrupt with the higher priority. interrupt levels can be set in the range 1 to 3. however, the cpu does not accept interrupt requests set to interrupt level 3. m example of multiple interrupts as an example of multiple interrupt processing, assume that an external interrupt has a higher priority than the timer interrupt. the timer interrupt is set to level 2 and the external interrupt is set to level 1. figure 3.4-3 "example of multiple interrupts" shows the processing when the external interrupt occurs during execution of timer interrupt processing. figure 3.4-3 example of multiple interrupts ? during execution of timer interrupt processing, the interrupt level bits in the condition code register (ccr:il1, il0) are automatically set to the same value as the interrupt level setting register (ilr1, ilr2, ilr3, ilr4) corresponding to the timer interrupt (level 2 in this example). if the interrupt request set to higher interrupt level (level 1 in this example) occurs at this time, the interrupt processing has priority. ? to temporarily disable multiple interrupts during the timer interrupt, the interrupt enable flag in the condition code register is set to "interrupts disabled" (ccr: i = "0") or the interrupt level bits (il1, il0) set to "00". ? on execution of the interrupt return instruction (reti) at the completion of interrupt processing, the cpu restores the program counter (pc) and program status (ps) values saved on the stack and resumes execution of the interrupted program. restoring the program status (ps) returns the condition code register (ccr) to the value prior to the interrupt. (4) (5) (6) (7) (1) (2) (3) (8) main program initialize peripheral timer interrupt occurs restart main program interrupt level 2 (ccr:il1, il0 = "10") timer interrupt processing external interrupt halt restart timer interrupt timer interrupt returns processing interrupt level 1 (ccr:il1, il0 = "01") external interrupt processing external interrupt processing external interrupt returns occurs
47 3.4 interrupts 3.4.4 interrupt processing time the total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing). the maximum time for this process is 30 instruction cycles. n interrupt processing time when an interrupt request occurs, the time until the interrupt is accepted and the interrupt processing routine is executed includes the interrupt request sampling time and the interrupt handling time. m interrupt request sampling time whether or not an interrupt request has occurred is determined by sampling and testing for interrupt requests during the final cycle of each instruction. therefore, the cpu is unable to identify interrupt requests during execution of an instruction. the longest delay occurs when an interrupt request is generated immediately after starting execution of a divu instruction, which has the longest instruction cycles (21 instruction cycles). m interrupt handling time nine instruction cycles are required to perform the following preparation for interrupt processing after the cpu accepts an interrupt request: ? save the program counter (pc) and program status (ps). ? set the top address of the interrupt processing routine (the interrupt vector) in the pc. ? update the interrupt level bits (ps:ccr: il1, il0) in the program status (ps). figure 3.4-4 "interrupt processing time" shows the interrupt processing time. figure 3.4-4 interrupt processing time the total interrupt processing time of 21 + 9 = 30 instruction cycles is required if an interrupt request occurs immediately after starting execution of a divu instruction, which has the longest instruction cycles (21 instruction cycles). if, on the other hand, the program does not use the divu or mulu instructions, the maximum interrupt processing time is 6 + 9 = 15 instruction cycles. the time of one instruction cycle changes with the clock mode and the main clock frequency as selected by the "speed-shift" (gear) function. see section 3.7 "clock" for details. cpu operation interrupt waiting time execution of a standard instruction interrupt request sampling time interrupt request occurs interrupt handling interrupt handling time (9 instruction cycles) interrupt processing routine : final cycle of instruction. interrupt requests are sampled at this timing.
48 chapter 3 cpu 3.4.5 stack operation during interrupt processing this section describes the saving of the register contents to the stack and restore operation during interrupt processing. n stack operation at start of interrupt processing the cpu automatically saves the current contents of the program counter (pc) and program status (ps) to the stack when an interrupt is accepted. figure 3.4-5 "stack operation at start of interrupt processing" shows the stack operation at the start of interrupt processing. figure 3.4-5 stack operation at start of interrupt processing n stack operation at interrupt return on execution of the interrupt return instruction (reti) at the completion of interrupt processing, the cpu performs the opposite processing to interrupt initiation, restoring first the program status (ps) and then the program counter (pc) from the stack. this returns the ps and pc to their states immediately prior to the start of the interrupt. note: the cpu does not automatically save the accumulator (a) or temporary accumulator (t) contents to the stack. use the pushw and popw instructions to save and restore a and t contents to and from the stack. h h h h h h 027c h 027d h 027e h 027f h 0280 h 0281 h address memory 0870 h ps e000 h pc 0280 h sp immediately before interrupt 08 h 70 h e0 h 00 h h h 027c h 027d h 027e h 027f h 0280 h 0281 h address memory 027c h sp 0870 h ps e000 h pc immediately after interrupt ps pc y t y t
49 3.4 interrupts 3.4.6 stack area for interrupt processing interrupt processing execution uses the stack area in ram. the contents of the stack pointer (sp) specifies the top address of the stack area. n stack area for interrupt processing the subroutine call instruction (call) and vector call instruction (callv) use the stack area to save and restore the program counter (pc). the stack area is also used by the pushw and popw instructions to temporarily save and restore registers. ? the stack area is located in ram along with the data area. ? initializing the stack pointer (sp) to the top address of ram and allocating data areas upwards from the bottom ram address is recommended. figure 3.4-6 "stack area for interrupt processing" shows the example of stack area setting. figure 3.4-6 stack area for interrupt processing reference: the stack area is used in the downward direction starting from a high address by functions such as interrupts, subroutine calls, and the pushw instruction. instructions such as return instructions (reti, ret) and the popw instruction release stack area in the upward direction. take care when the stack address is decreased by multiple interrupts or subroutine calls that the stack does not overlap the general-purpose register area or areas containing other data. general- purpose registers i/o ram access rom 0000 h 0080 h 0100 h 0200 h ffff h 0280 h recommended set value for sp data area stack area (when the top address of ram is 0280 h. ) prohibited
50 chapter 3 cpu 3.5 resets the resets has the following four types of reset source: ? external reset ? software reset ? watchdog reset ? power-on reset at reset, main clock oscillation stabilization delay time may or may not occur by the operating mode and option settings. n reset source m external reset inputting an "l" level to the external reset pin (rstx) generates an external reset. returning the reset pin to the "h" level wakes up the cpu from the external reset. when power is turned on to products with power-on reset or for external resets in stop mode, the reset operation is performed after the oscillation stabilization delay time has passed and the cpu wakes up from the external reset. external resets on products without power-on reset do not wait for the oscillation stabilization delay time. the external reset pin can also function as a reset output pin (optional). m software reset writing "0" to the software reset bit in the standby control register (stbc: rst) generates a four-instruction cycle reset. the software reset does not wait for the oscillation stabilization delay time. m watchdog reset the watchdog reset generates a four-instruction cycle reset if data is not written to the watchdog timer control register (wdtc) within a fixed time after the watchdog timer starts. the watchdog reset does not wait for the oscillation stabilization delay time. m power-on reset a reset is generated by power-on. the reset operation is performed after the oscillation stabilization delay time has passed. table 3.5-1 reset source reset source reset conditions external reset set the external reset pin to the "l" level. software reset write "0" to the software reset bit in the standby control register (stbc: rst). watchdog reset watchdog timer overflow power-on reset power is turned on (only on products with a power-on reset).
51 3.5 resets n main clock oscillation stabilization delay time and the reset source whether there will be an oscillation stabilization delay time depends on the operating mode when reset occurs, and the power-on reset option selected. following reset, operation always starts out in the normal main clock operating mode, regardless of the kind of reset it was, or the operating mode (the clock mode and standby mode) prior to reset. therefore, if reset occurs while the main clock oscillator is stopped or in a stabilization delay time, the system will be in a "main clock oscillation stabilization reset" state, and a clock stabilization period will be provided. if the device is set for no power-on reset, however, no main clock oscillation stabilization delay time is provided for power-on or external reset. in software or watchdog reset, if the reset occurs while the device is in main clock mode, no stabilization time is provided. if it occurs in the subclock mode, however, a stabilization time is provided since the main clock oscillation is stopped.table 3.5-2 "reset source and oscillation stabilization delay time" shows the relationships between the reset sources and the main clock oscillation stabilization delay time, and reset mode (mode fetch) operations. table 3.5-2 reset source and oscillation stabilization delay time reset source operating state reset operation and main clock oscillation stabilization delay time external reset *1 at power on, during stop mode, or subclock mode after the main clock oscillation stabilization delay time, if the external reset is waked up, reset is operated. *2 software and watchdog reset main clock mode after 4-instruction-cycle reset occurs, reset is operated. *3 subclock mode reset is operated after the main clock oscillation stabilization delay time. *2 power-on reset device enters main clock oscillation stabilization delay time at power on. reset is operated after delay time ends. *2 *1: no oscillation stabilization delay time is required for external reset while main clock mode is operating. reset is operated after external reset is waked up. *2: if the reset output option is selected, "l" is output at rstx pin during the main clock oscillation stabilization delay time. *3: if the reset output option is selected, "l" level is output at rstx pin during 4-instruction-cycle.
52 chapter 3 cpu 3.5.1 reset flag register (rsfr) the reset flag register (rsfr) can be used to identify the reset generation sources when a reset occurs. n reset flag register (rsfr) figure 3.5-1 reset flag register (rsfr) ponr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 e h address xxxxxxxx b initial value wdog rr erst sftr ponr power-on reset flag rr wdog watchdog reset flag sftr software reset flag operation is not affected operation is not affected operation is not affected operation is not affected r: read only x: undefined the reset source is a software reset. 0 1 read write the reset source is a watchdog reset. 0 1 read write the reset source is an external reset. 0 1 read write the reset source is a power-on reset. 0 1 read write erst external reset flag
53 3.5 resets note: each reset source flag is set when each reset source occurs. when each reset source flag register is read, each bit of the reset source flag register is cleared. thus, determine the reset source by reading this register using the initialization routine after the reset. table 3.5-3 explanation of the functions of each bit of the reset flag register (rsfr) bit name function bit 7 ponr: power-on reset flag "1" is set when a power-on reset occurs. "1" is set after power-on. this register is cleared to "0" by reading it. a write operation to this register is insignificant. bit 6 erst: external reset flag "1" is set when an external reset occurs. "1" is set to the software reset flag while retaining each reset flag if each reset flag is set before the external reset flag is set. this register is cleared to "0" by reading it. a write operation to this register is insignificant. bit 5 wdog: watchdog reset flag "1" is set when a watchdog reset occurs. "1" is set to the watchdog reset flag while retaining each reset flag if each reset flag is set before the watchdog reset flag is set. this register is cleared to "0" by reading it. a write operation to this register is insignificant. bit 4 sftr: software reset flag "1" is set when a software reset occurs. "1" is set to the software reset flag while retaining each reset flag if each reset flag is set before the software reset flag is set. this register is cleared to "0" by reading it. a write operation to this register is insignificant. bit 3 bit 2 bit 1 bit 0 unused bits the read value is undefined. writing has no effect on operation.
54 chapter 3 cpu 3.6 external reset pin inputting an "l" level to the external reset pin generates a reset. if products are set to with the reset output (optional), the pin outputs an "l" level depending on internal reset sources. n block diagram of external reset pin the external reset pin (rstx) on products with the reset output is a hysteresis input type and n-ch open-drain output type with a pull-up resistor. the external reset pin on products without a reset output option is only for the reset input.figure 3.6-1 "block diagram of external reset pin" shows the block diagram of the external reset pin. figure 3.6-1 block diagram of external reset pin n external reset pin functions inputting an "l" level to the external reset pin (rstx) generates an internal reset signal. on products with the reset output, the pin outputs an "l" level depending on internal reset sources or during the oscillation stabilization delay time due to an external reset. software reset, watchdog reset, and power-on reset are classed as internal reset sources. note: the external reset input accepts asynchronous with the internal clock. therefore, initialization of the internal circuit requires a clock. especially when an external clock is used, a clock is needed to be input at the reset. p-ch n-ch rst pin pull-up resistor approx. 50 k w /5.0v input buffer internal reset signal internal reset source
55 3.6 external reset pin 3.6.1 reset operation when the cpu wakes up from a reset, the cpu selects the read address of the mode data and reset vector according to the mode pin settings, then performs a mode fetch. the mode fetch is performed after the oscillation stabilization delay time has passed when power is turned on to a product with power-on reset, or on wake-up from subclock or stop mode by a reset. if reset occurs during a write to ram, the contents of the ram address cannot be assured. n overview of reset operation figure 3.6-2 reset operation flow diagram during reset mode fetch (reset operation) normal operation (run state) software reset watchdog reset no no external reset input yes yes power-on, subclock wakes up from external fetch mode data fetch reset vector fetch the instruction code from the address indicated by the reset vector and begin execution. power-on reset main clock oscillation stabilization delay reset operation reset? yes in subclock mode? main clock oscillation stabilization delay reset state no or stop mode? state main clock oscillation stabilization delay reset state
56 chapter 3 cpu n mode pins the mb89570 series devices are single-chip mode devices. the mode pins (mod1 and mod0) must be tied to vss. the mode pin settings determine whether the mode data and reset vector are read from internal rom. do not change the mode pin settings, even after the reset has completed. n mode fetch when the cpu wakes up from a reset, the cpu reads the mode data and reset vector from internal rom. m mode data (address: fffd h ) always set the mode to "00 h " (single-chip mode). m reset vector (address: fffe h (upper), ffff h (lower)) contains the address where execution is to start after completion of the reset. the cpu starts executing instructions from the address contained in the reset vector. n oscillation stabilization delay reset state on products with power-on reset, the reset operation for a power-on reset or external reset in subclock or stop (main/sub) mode starts after the main clock oscillation stabilization delay time selected by the stabilization delay time option. if the cpu has not woken up from the external reset input when the delay time completes, the reset operation does not start until the cpu wakes up from external reset. as the oscillation stabilization delay time is also required when an external clock is used, a reset requires that the external clock is input. the main clock oscillation stabilization delay time is timed by the timebase timer. on products without power-on reset, the oscillation stabilization delay reset state is not used. therefore, for such products, hold the external reset pin (rstx) at the "l" level to disable the cpu operation until the source oscillation stabilizes. n effect of reset on ram contents the contents of ram are unchanged before and after a reset other than power-on reset. if an external reset is input close to a write timing, however, the contents of the write address cannot be assured. for this reason, all ram locations being used should be initialized following reset.
57 3.6 external reset pin 3.6.2 pin states during reset reset initialized the pin states. n pin states during reset when a reset source occurs, with a few exceptions, all i/o pins (peripheral pins) go to the high- impedance state and the mode data is read from internal rom. n pin states after reading mode data with a few exceptions, the i/o pins remain in the high-impedance state immediately after reading the mode data. note: for devices connected to pins that change to high-impedance state when a reset source occurs take care that malfunction does not occur due to the change in the pin states.
58 chapter 3 cpu 3.7 clock dual clock oscillation circuits are contained in the clock generator. by connecting each external resonator, the high-speed main clock and low-speed subclock are generated independently (oscillator source). a clock generated externally can also be input. the speed and supply of the dual clock is controlled by the clock controller according to the clock mode and standby mode. n clock supply map the clock oscillation and the supply to cpu and peripheral circuits (peripheral functions) are controlled by the clock controller. thus, the operating clock of cpu and peripheral circuits are affected by switching between the main clock and the subclock (clock mode), speed switching of the main clock (gear function), and the standby mode (sleep/stop/clock). the divide-by output of the free-run counter of the clock for peripheral circuits is supplied to each peripheral function. the divide-by output of the timebase timer operating at divide-by-two oscillation of the main clock oscillation and peripheral functions to which divide-by output of the watch prescaler operating at the subclock is supplied are available and are not affected by the gear function. the following figure 3.7-1 "clock supply map" shows a clock supply map.
59 3.7 clock figure 3.7-1 clock supply map divide-by-4 divide-by-8 divide-by-16 divide-by-64 timebase timer supply to cpu supply to peripheral circuits 1tinst 1tinst free-run counter watch prescaler uart/sio i 2 c bus (multi address) oscillation stabilization wait control watchdog timer main clock oscillation circuit oscillation control pin pin x0 x1 subclock oscillation circuit pin pin x0a x1a clock mode stop mode f ch f cl clock controller peripheral functions f ch : main clock oscillation f cl : subclock oscillation t inst: instruction cycle *1: not affected by the clock mode and gear function. *2: the operating speed is affected by the clock mode and gear function. *3: operations stop if the clock (main or sub), which is the source of oscillation, stops. divide-by-two divide- by-two gear function clock mode sleep/stop/clock oscillation stabilization wait stop clock i 2 c bus comparator lcd controller/driver 8/16-bit timer pin ec 16-bit timer
60 chapter 3 cpu 3.7.1 clock generator the permission and stop of oscillation of the main clock and subclock are controlled by the clock mode and stop mode. n clock generator m crystal resonator or ceramic resonator make connections as shown in figure 3.7-2 "connection example of the crystal and ceramic resonator". figure 3.7-2 connection example of the crystal and ceramic resonator m external clock connect the external clock to the x0 pin as shown in figure 3.7-3 "connection example of the external clock" and open the x1 pin. if the subclock should be supplied externally, connect the external clock to the x0a pin and open the x1a pin. note that the mb89pv570 outputs "l" from the x0a pin in sub-stop mode. x0 x1 cc dual clock system main clock oscillation circuit subclock oscillation circuit x0 x1 x0a x1a single clock system open cc cc main clock oscillation circuit subclock oscillation circuit x0a x1a mb89570 series mb89570 series r
61 3.7 clock figure 3.7-3 connection example of the external clock note: in mb89pv570, "l" is output from the x0a pin in sub-stop mode. if the subclock is supplied from an external clock, care must be taken to ensure that "h" is not applied to the x0a pin in sub-stop mode. x0 x1 x0a x1a x0 x1 x0a x1a open open open open mb89570 series mb89570 series main clock oscillation circuit subclock oscillation circuit dual clock system single clock system main clock oscillation circuit subclock oscillation circuit
62 chapter 3 cpu 3.7.2 clock controller the clock controller is made up of the following seven blocks: ? main clock oscillation circuit ? subclock oscillation circuit ? system clock selector ? clock control circuit ? oscillation stabilization wait time selector ? system clock control register (sycc) ? standby control register (stbc) n block diagram of the clock controller figure 3.7-4 "block diagram of the clock controller" shows a block diagram of the clock controller. figure 3.7-4 block diagram of the clock controller subclock oscillation circuit standby control register (stbc) system clock control register (sycc) oscillation stabilization wait time selector main clock oscillation circuit clock supply stop to cpu pin state stop sleep clock clock for watch prescaler clock for timebase timer supply to cpu supply to peripheral circuits clock designation prescaler divide-by-4 divide-by-8 divide-by-16 divide-by-64 selector selector tmd stp slp spl rst cs1 cs0 wt0 scs scm wt1 system clock selector main clock control subclock control 2 from timebase timer from watch prescaler f ch : main clock oscillation f cl : subclock oscillation t inst: instruction cycle clock control circuit operation allowed operation allowed 1 tinst 1 tinst divide-by-two divide-by-two f ch f ch f ch
63 3.7 clock m main clock oscillation circuit oscillation circuit of the main clock. this circuit stops oscillation in main stop mode and subclock mode. m subclock oscillation circuit oscillation circuit of the subclock. this circuit always oscillates in a mode other than sub-stop mode. m system clock selector one type is selected from the four clocks and the subclocks obtained by dividing the oscillation of the main clock to supply it to the clock control circuit. m clock control circuit the operating clock supply to cpu and each peripheral circuit is controlled according to normal operation (run) and standby modes (sleep, stop, clock). the clock controller stops the supply of clocks to cpu until the clock supply stop signal of the oscillation stabilization wait time selector is released. m oscillation stabilization wait time selector one wait time is selected from the four kinds of oscillation stabilization wait time for the main clock created by the timebase timer and the oscillation stabilization wait time for the subclock created by the watch prescaler for the clock mode, standby mode, and reset and is output as the clock supply stop signal to cpu. m system clock control register (sycc) the selection of the clock mode and main clock speed is performed, and the selection and state confirmation of the oscillation stabilization wait time of the main clock is performed. m standby control register (stbc) the transition from normal operation (run) to standby mode, pin state settings in stop mode or watch mode, and software reset are performed.
64 chapter 3 cpu 3.7.3 system clock control register (sycc) the system clock control register (sycc) is used to switch the main clock and the subclock, to select the speed of the main clock, and to select the oscillation stabilization wait time. n structure of the system clock control register (sycc) figure 3.7-5 structure of the system clock control register (sycc) scm bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 7 h address xxxmm100 b initial value r r/w scs wt1 wt0 cs0 cs1 r/w scm system clock monitor bit subclock (the main clock is stopped or waiting for oscillation stabilization) main clock 0 1 scs system clock select bit select the subclock mode (32 khz) select the main clock mode 0 1 wt1 oscillation stabilization wait time select bit 0 0 1 1 wt0 0 1 0 1 setting prohibited about 2 14 / f ch (about 1.63 ms) about 2 17 / f ch (about 13.1 ms) about 2 18 / f ch (about 26.2 ms) cs1 main clock speed select bit instruction cycle (for f ch = 10 mhz) cs0 64/f ch (6.4 s) 16/f ch (1.6 s) 8/f ch (0.8 s) 4/f ch (0.4 s) f ch : main clock oscillation r/w : read/write enabled r : read only x : undefined m : defined by option settings : initial value r/w 0 0 1 1 0 1 0 1 r/w r/w main clock oscillation stabilization wait time by timebase timer output (for f ch = 10 mhz)
65 3.7 clock *: options can be selected only for MB89577. table 3.7-1 explanation of the functions of each bit of the system clock control register (sycc) bit name function bit 7 scm: system clock monitor bit ? bit to check the current clock mode (operating clock) ? if the bit is "0", the system is operating in subclock mode (the main clock is stopped or waiting for oscillation stabilization to make a transition to the main clock mode). ? if the bit is "1", the system is operating in main clock mode. [reference:] this bit is read-only. write operation to this bit has no significance and does not affect operations. bit 6 bit 5 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 4 bit 3 wt1, wt0: oscillation stabilization wait time select bits ? bits to select the oscillation stabilization wait time of the main clock ? the oscillation stabilization wait time selected by these bits is taken when making a transition from the subclock mode to the main clock mode, or returning to normal operation from the main stop mode by an external interrupt. ? the initial values of these bits are selected by option settings *. thus, if an oscillation stabilization wait time is taken for a reset, the oscillation stabilization wait time selected by option settings is taken. note: do not rewrite these bits simultaneously when switching from the subclock to the main clock (scs=1 --> 0). before rewriting the bits, check that the oscillation stabilization is not waited upon using the scm bit. bit 2 scs: system clock select bit ? bit to specify the clock mode ? a transition from the main clock mode to the subclock mode is caused by writing "0" into this bit. ? if "1" is written into this bit, the transition from the subclock mode to the main clock mode occurs after taking the oscillation stabilization wait time set by the wt1 and wt0 bits. note: if the single clock system option is selected, this bit has no significance. set always "1". bit 1 bit 0 cs1, cs0: main clock speed select bits ? bit to select the clock speed in main clock mode. ? four different speeds of the operating clock can be selected for cpu and each peripheral function (gear function). however, the operating clock of the timebase timer and watch prescaler is not affected by these bits.
66 chapter 3 cpu n instruction cycle (t inst ) the instruction cycle (minimum execution time) can be selected from the 1/4, 1/8, 1/16, or 1/64 of the main clock and the divide-by-two of the subclock (32.768 khz) using the system clock select bit (scs) and main clock speed select bits (cs1, cs0) of the sycc register. the instruction cycle at the maximum speed (sycc: scs=1, cs1, cs0=11 b ) in main clock mode is 4/f ch = about 0.4 m s if the main clock oscillation (f ch ) is 10 mhz. the instruction cycle in subclock mode (scs=0) is 2/f cl = about 61.0 m s if the subclock oscillation (f cl ) is 32.768 khz.
67 3.7 clock 3.7.4 clock modes the main clock mode and subclock mode are available as the clock mode. in main clock mode, the main clock is the main operating clock. the speed of the main clock can be switched by selecting from four kinds of clocks created by dividing its oscillation (gear function). in subclock mode, the oscillation of the man clock is stopped and the subclock alone becomes the operating clock. n operating state of the clock mode in each clock mode, a transition can be made to the standby mode corresponding to each mode. for the standby mode, see section 3.8 "standby mode (low power consumption)". table 3.7-2 operating state of the clock mode clock mode main clock speed sycc register (cs1, cs0) standby mode clock generation operation clock in each section release source of standby mode (other than resets) main sub cpu timebas e timer each peripheral watch prescaler main clock mode (1.1) run oscillation oscillation f ch /4 f ch /2 f ch /4 f cl various interrupt requests sleep stop stop stop stop stop external interrupt (1.0) run oscillation oscillation f ch /8 f ch /2 f ch /8 f cl various interrupt requests sleep stop stop stop stop stop external interrupt (0.1) run oscillation oscillation f ch /16 f ch /2 f ch /16 f cl various interrupt requests sleep stop stop stop stop stop external interrupt (0.0) run oscillation oscillation f ch /64 f ch /2 f ch /64 f cl various interrupt requests sleep stop stop stop stop stop external interrupt subclock mode - run stop oscillation f cl stop (*1) f cl f cl various interrupt requests sleep stop stop stop stop stop external interrupt watch mode stop oscillation stop stop (*1) stop f cl external interrupt, watch interrupt f ch : main clock oscillation f cl : subclock oscillation *1: since the timebase timer is operated by the main clock, it stops operation in subclock mode. high speed low speed
68 chapter 3 cpu n gear function (function for switching the speed of the main clock) four different main clock speeds can be selected by writing "00 b " to "11 b " into the main clock speed select bits (sycc: cs1, cs0) of the system clock control register. cpu and each peripheral circuit operate at the switched main clock speed. however, the timebase timer and watch prescaler are not affected by the gear function. by reducing the main clock speed, power consumption can be reduced. n operation in main clock mode in normal operation in main clock mode (main run mode), both the main clock and subclock oscillate. the watch prescaler is operated by the subclock, whereas cpu, the timebase timer, and other peripheral circuits are operated by the main clock. the speed of the main clock can be switched to a value other than that of the timebase timer during operation in main clock mode (gear function). a transition to the main sleep mode or main stop mode is enabled by specifying the standby mode. operation always starts in main run mode regardless of the type of reset that occurs (release by the reset in each operation mode). m transition from the main clock mode to the subclock mode a transition from the main clock mode to the subclock mode is caused by writing "0" into the system clock select bit (sycc: scs) of the system clock control register. the current operating clock can be checked by reading the system clock monitor bit (sycc: scm) of the system clock control register. to make a transition to the subclock mode, for example, just after power-on, it is necessary to wait at least the subclock oscillation stabilization wait time created by the watch prescaler using software before making a transition.
69 3.7 clock n operation in subclock mode in normal operation in subclock mode (sub run mode), the oscillation of the main clock is stopped and only the subclock is used for operation. by operating in a low speed clock, power consumption can be reduced. all functions other than the timebase timer operate as in the main clock mode. a transition to the sub-sleep mode, sub-stop mode, or watch mode is enabled by specifying the standby mode during operation in subclock mode. m return from the subclock mode to the main clock mode a return from the subclock mode to the main clock mode is caused by writing "1" into the system clock select bit (sycc: scs) of the system clock control register. however, operation in main clock mode starts only after the oscillation stabilization wait time of the main clock passes. the oscillation stabilization wait time can be selected from three different wait times using the oscillation stabilization wait time select bits (sycc: wt1, wt0) of the system clock control register. note: do not rewrite the oscillation stabilization wait time select bits (sycc: wt1, wt0) simultaneously by switching from the subclock to the main clock. also, do not rewrite the bits when the oscillation stabilization of the main clock is waited upon. in such cases, rewrite the bits after checking that the operating clock has been switched to the main clock (sycc: scm=1) by the system clock monitor bit. to return to the main clock mode from the subclock mode using a reset, take the oscillation stabilization wait time of the main clock.
70 chapter 3 cpu 3.7.5 oscillation stabilization wait time if the main clock is operated in main run mode from a state in which the main clock is stopped, for example, when the power is turned on, or in main stop mode or subclock mode, it is necessary to take the oscillation stabilization wait time of the main clock. likewise, the oscillation stabilization wait time of the subclock is needed in sub-stop mode because the oscillation of the subclock is stopped. n oscillation stabilization wait time ceramic and crystal resonators generally take several ms to several dozens of ms to oscillate steadily in natural frequency after starting oscillation. thus, cpu operation must be prohibited just after starting oscillation. the clock should be supplied to cpu only when the oscillation is sufficiently stable after the passage of the oscillation stabilization wait time. since the time needed to stabilize oscillation is dependent on the type (such as the crystal and ceramic) of resonator connected to the oscillator (clock generator), an oscillation stabilization wait time appropriate to the resonator to be used must be selected. figure 3.7-6 "oscillator operation after oscillation starts" shows an oscillator operation just after the oscillation starts. figure 3.7-6 oscillator operation after oscillation starts n oscillation stabilization wait time of the main clock to start operation in main clock mode from a state in which the main clock is stopped, the oscillation stabilization wait time of the main clock must be taken. the oscillation stabilization wait time of the main clock is a time interval counted from when the counter of the timebase timer is cleared until the overflow of the specified bit occurs. m oscillation stabilization wait time during operation one of the four kinds of oscillation stabilization wait time when returning to the main run mode from the main stop mode by an external reset or when making a transition from the subclock mode to the main clock mode can be selected using the oscillation stabilization wait time select bits (sycc: wt1, wt0) of the system clock control register. ( ) oscillation stabilization wait time normal operation, return from the stop mode, or reset operation oscillation start x1 oscillation stable resonator oscillation time
71 3.7 clock m oscillation stabilization wait time during reset the oscillation stabilization wait time during reset (initial value of wt1 and wt0) can be selected by option settings. the oscillation stabilization wait time must be taken for (multiple) resets in subclock mode, a power-on reset, and the stop mode release by an external reset. table 3.7-3 "operation start conditions and oscillation stabilization wait time of the main clock mode" lists the relations between the operation start conditions and oscillation stabilization wait time of the main clock mode. n oscillation stabilization wait time of the subclock a certain oscillation stabilization wait time (2 15 /f cl , f cl : subclock oscillation) of the subclock must be taken when returning to the sub run mode (subclock oscillation is started) from the sub-stop mode (state in which oscillation of the subclock is stopped) by an external reset. the oscillation stabilization wait time of the subclock is a time interval from the start of operation in a state in which the watch prescaler is cleared until an overflow occurs. since the oscillation stabilization wait time of the subclock is needed during power-on, wait at least the subclock oscillation stabilization wait time using software to make a transition to the subclock mode after power-on. table 3.7-3 operation start conditions and oscillation stabilization wait time of the main clock mode start conditions for main clock operation during power-on during subclock mode release from main stop mode transition from the subclock mode to the main clock mode (sycc: scs (*1) =1) external reset software reset and watchdog timer external reset external interrupt oscillation stabilization wait time selection option settings (*3) sycc:wt1, wt0 (*2) *1: system clock select bit of the system clock control register *2: oscillation stabilization wait time select bit of the system clock control register *3: only in MB89577, options of the initial value of "sycc: wt1, wt0" can be selected.
72 chapter 3 cpu 3.8 standby mode (low power consumption) the sleep mode, stop mode, and watch mode are available as the standby mode. a transition to the standby mode is caused by settings of the standby control register (stbc) both in main clock mode and subclock mode. in main clock mode, transitions to the sleep mode and stop mode are possible. in subclock mode, transitions to the sleep mode, stop mode, and watch mode are possible. power consumption can be reduced by stopping operations of cpu and peripheral functions using the standby mode. this section describes the relations between the standby mode and clock mode, and the operating states of each section in standby mode. n standby mode in clock mode, power consumption is reduced by reducing the operating clock of cpu and peripheral circuits such as switching of the main clock and subclock or switching of the main clock speed (gear function). in standby mode, however, power consumption is reduced by the clock supply stop (sleep mode) to cpu by the clock controller, clock supply stop (watch mode) to cpu and peripheral circuits, or stop of the oscillation itself (stop mode). m main sleep mode the main sleep mode is a mode which stops operations of cpu and the watchdog timer. peripheral functions excluding the watch prescaler operate on the main clock (part of the functions can operate on the subclock). m sub-sleep mode the sub-sleep mode is a mode which stops the main clock oscillation, cpu operations, and watchdog timer and timebase timer operations. peripheral functions operate on the subclock. m main stop mode the main stop mode is a mode which stops operations of cpu and peripheral functions. the main clock stops oscillation, but the subclock continues oscillation. in this mode, all functions are stopped excluding external interrupts, count operations of the watch prescaler, and some of the functions that run with the subclock. m sub-stop mode the sub-stop mode is a mode which stops all functions other than external interrupts. the main clock and the subclock both stop oscillation. m watch mode the clock mode is a mode a transition to which is possible only from the subclock mode. all functions other than the watch prescaler (watch interrupt), external interrupts, and part of the functions operating on the subclock stop.
73 3.8 standby mode (low power consumption) 3.8.1 operating state in standby mode this section describes the operating states of cpu and peripheral functions in standby mode. n operating state in standby mode m pin state in standby mode most i/o pins can, independent of the clock mode, retain the state just before transition to the stop or watch mode or can be put into high impedance using the pin state designate bit (stbc: spl) of the standby control register. table 3.8-1 the operating states of cpu and peripheral functions in standby mode operation mode main clock mode subclock mode function run sleep stop (spl=0) stop (spl=1) run sleep stop (spl=0) stop (spl=1) clock main clock operating operating stopped stopped stopped stopped stopped stopped stopped subclock operating operating operating operating operating operating stopped stopped operating cpu instruction operating stopped stopped stopped operating stopped stopped stopped stopped rom operating retained retained retained operating retained retained retained retained ram peripheral functions i/o port operating retained retained retained operating retained retained retained retained timebase timer operating operating stopped stopped stopped stopped stopped stopped stopped watchdog timer operating stopped stopped stopped operating (*4) stopped stopped stopped stopped multi-address i 2 c bus operating operating stopped stopped operating operating stopped stopped stopped i 2 c bus operating operating stopped stopped operating operating stopped stopped stopped uart/sio operating operating stopped stopped operating operating stopped stopped stopped comparator operating operating operating operating operating operating operating operating operating a/d converter operating operating stopped stopped operating operating stopped stopped stopped external interrupt operating operating operating operating operating operating operating operating operating watch prescaler operating operating operating (*1) operating (*1) operating operating stopped stopped operating lcd controller/driver operating operating operating (*2) operating (*2) operating (*2) operating (*2) stopped stopped operating (*2) d/a converter operating operating stopped stopped operating operating stopped stopped stopped 8/16-bit timer operating operating stopped stopped operating operating stopped stopped stopped 16-bit timer operating operating stopped stopped operating operating stopped stopped stopped pin operating retained retained hi-z operating retained retained hi-z retained how to release reset/ various interrupts reset/ various interrupts reset/ various interrupts reset/ various interrupts reset/ various interrupts reset/ various interrupts reset/ various interrupts reset/ various interrupts reset/ various interrupts *1: the watch prescaler carries out the count operation, but no watch interrupt occurs. *2: the subclock is selected as the operating clock. operation permission is required in watch mode.
74 chapter 3 cpu 3.8.2 sleep mode this section describes the operations in sleep mode. n operations in sleep mode m transition to the sleep mode the sleep mode is a mode which stops the operating clock of cpu. cpu stops by retaining the contents of the registers and ram just before transition to the sleep mode, but peripheral functions other than the watchdog timer continue their operations. however, since the main clock oscillation stops in subclock mode, the timebase timer which uses the divide-by-two of the main clock oscillation as its count clock does not operate. a transition to the sleep mode is caused by writing "1" into the sleep bit (stbc: slp) of the standby control register. if an interrupt has occurred when "1" is written into the slp bit, the write operation is ignored and execution of instructions continues without transition to the sleep mode (no transition to sleep mode after the interrupt). m sleep mode release the sleep mode is released by a reset or an interrupt from the peripheral functions. if a reset occurs in sub-sleep mode, the reset operation is performed after taking the oscillation stabilization wait time of the main clock. pin states are initialized by the reset operation. if an interrupt request whose interrupt level is higher than "11" comes from a peripheral function or external interrupt circuit, the sleep mode is released regardless of the interrupt enable flag (ccr: i) or interrupt level bit (ccr: il1, 0) of cpu. after the release, normal interrupt operations are performed. if an interrupt can be accepted, interrupt processing is performed. if no interrupt can be accepted, processing starts with the instruction following the instruction executed just before the transition to sleep mode.
75 3.8 standby mode (low power consumption) 3.8.3 stop mode this section describes the operations in stop mode. n operations in stop mode m transition to the stop mode the stop mode is a mode which stops the oscillation. contents of the registers and ram just before transition to the stop mode are retained and most functions are stopped. in main clock mode, the main clock stops the oscillation, but the subclock continues the oscillation. thus, though the count operation of the watch prescaler and part of the functions operating on the subclock continue their operations, other peripheral functions and cpu, excluding the external interrupt circuits, stop operations. in subclock mode, both the main clock and subclock stop oscillation, and all functions other than the external interrupt circuits stop their functions. thus, data can be retained with minimum power consumption. a transition to the stop mode is caused by writing "1" into the stop bit (stbc: stp) of the standby control register. at this time, if the pin state designate bit (stbc: spl) is "0", the states of external pins are retained. if the bit is "1", external pins are put into high impedance. if an interrupt request has occurred when "1" is written into the stp bit, the write operation is ignored and execution of instructions continues without making a transition to the stop mode (no transition to the stop mode occurs even after interrupt processing is completed). to make a transition to the stop mode in the main clock mode, prohibit (tbtc: tbie=0) the interrupt request output of the timebase timer if necessary. likewise, to make a transition to the stop mode in subclock mode, prohibit (wpcr: wie=0) the watch interrupt request output of the watch prescaler. m stop mode release the stop mode can be released by a reset or external interrupt. if a reset occurs in stop mode, the reset operation is performed after taking the oscillation stabilization wait time of the main clock. pin states are initialized by the reset. if an interrupt request whose interrupt level is higher than "11" comes from an external interrupt circuit in stop mode, the stop mode is released regardless of the interrupt enable flag (ccr: i) and interrupt level bits (ccr: il1, 0) of cpu. since peripheral functions are stopped in stop mode, no interrupt requests other than external interrupts occur. though the watch prescaler operates in main stop mode, no watch interrupts occur. if the stop mode is released, a normal interrupt operation is performed following the passage of the oscillation stabilization wait time. if the interrupt is accepted, interrupt processing is performed. if the interrupt is not accepted, execution starts with the instruction following the instruction executed just before transition to the stop mode. if the stop mode is released by an external interrupt, part of the peripheral functions restarts halfway through their operations. thus, for example, the first interval time of the interval timer function is undefined. each peripheral function should be initialized after returning from the stop mode.
76 chapter 3 cpu note: the stop mode release by an interrupt can only be caused by an interrupt request of the external interrupt circuits.
77 3.8 standby mode (low power consumption) 3.8.4 watch mode this section describes the operations in watch mode. n operations in watch mode m transition to the watch mode the watch mode is a mode which stops the operating clock of cpu and main peripheral circuits. a transition to the watch mode is only possible from the subclock mode (the main clock oscillation is stopped). contents of the registers and ram just before transition to the watch mode are retained and most functions other than the watch prescaler (watch interrupt), external interrupt circuits, and part of the functions operating on the subclock are stopped. thus, data can be retained with very low power consumption. a transition to the watch mode is caused by writing "1" into the clock bit (stbc: tmd) of the standby control register when the subclock mode is set by the system clock select bit of the system clock control register. if the pin state designate bit (stbc: spl) of the standby control register during transition to the watch mode is "0", the external pin states are retained. if the bit is "1", external pins are put into high impedance. if an interrupt request has occurred when "1" is written into the tmd bit, the write operation is ignored and execution of instructions continues without making a transition to the watch mode (no transition to the watch mode occurs even after interrupt processing is completed). m watch mode release the watch mode can be released by a reset, watch interrupt, or external interrupt. if a reset occurs in watch mode, the reset operation is performed after taking the oscillation stabilization wait time of the main clock. pin states are initialized by the reset. if an interrupt request whose interrupt level is higher than "11" comes from the watch prescaler or an external interrupt circuit in watch mode, the watch mode is released regardless of the interrupt enable flag (ccr: i) and interrupt level bits (ccr: il1, 0) of cpu. since most peripheral functions other than the watch prescaler are stopped in watch mode, no interrupt requests other than watch interrupts and external interrupts occur. after releasing the watch mode, a normal interrupt operation is performed. if the interrupt is accepted, interrupt processing is performed. if the interrupt is not accepted, execution starts with the instruction following the instruction executed just before transition to the watch mode. if the watch mode is released, part of the peripheral functions restarts halfway through their operations. thus, for example, the first interval time of the interval timer function is undefined. each peripheral function should be initialized after returning from the watch mode.
78 chapter 3 cpu 3.8.5 standby control register (stbc) the standby control register (stbc) is used to make a transition to the sleep mode/ stop mode/watch mode, set the pin states in watch mode, and reset software. n standby control register (stbc) figure 3.8-1 standby control register (stbc) stp bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 8 h address 00010xxx b initial value spl w r/w slp rst stp stop bit "0" is always read no effects on operations transition to the stop mode 0 1 read write tmd ww slp sleep mode "0" is always read no effects on operations transition to the sleep mode 0 1 0 1 read write spl pin state designate bit retain external pin states just before if in stop mode put external pins into high impedance if in stop mode 0 1 rst software reset bit "1" is always read generation of the reset signal of four instruction cycles 1 read write 0 tmd watch bit "0" is always read no effects on operations transition to the watch mode read write valid only in subclock mode (sycc: scs=0) r/w : read/write enabled w : write only - : unused x : undefined : initial value w no effects on operations
79 3.8 standby mode (low power consumption) table 3.8-2 explanation of the functions of each bit of the standby control register (stbc) bit name function bit 7 stp: stop bit ? bit to specify the transition to the stop mode ? a transition to the stop mode is caused by writing "1" into this bit. ? operations are not affected if "0" is written into this bit. ? when this bit is read, "0" is always read. bit 6 slp: sleep bit ? bit to specify the transition to the sleep mode ? a transition to the sleep mode is caused by writing "1" into this bit. ? ? operations are not affected if "0" is written into this bit. ? when this bit is read, "0" is always read. bit 5 spl: pin state designate bit ? bit to specify the external pin state in stop mode and watch mode ? if "0" is written into this bit, the external pin state (level) when making a transition to the stop or watch mode is retained. ? if "1" is written into this bit, the external pins are put into high impedance when making a transition to the stop or watch mode (the pins are raised to the "h" level if "pull- up resistor present" is selected in the pull-up setting register). ? this bit is set to "0" by a reset. bit 4 rst: software reset bit ? bit to specify the software reset ? an internal reset source in four instruction cycles caused by writing "0" into this bit. ? operations are not affected if "1" is written into this bit. ? when this bit is read, "1" is always read. [reference:] if the software reset is triggered in subclock mode, operation starts in main clock mode after taking the oscillation stabilization wait time. thus, the reset signal is output during oscillation stabilization wait time. bit 3 tmd: watch bit ? bit to specify the transition to the watch mode ? write operation to this bit is valid only in subclock mode (sycc: scs=0). ? a transition to the watch mode is caused by writing "1" into this bit. ? operations are not affected if "0" is written into this bit. ? when this bit is read, "0" is always read. bit 2 bit 1 bit 0 unused bits ? the read value is undefined. ? writing has no effect on operation.
80 chapter 3 cpu 3.8.6 state transition diagram 1 (dual clock) this section shows a state transition diagram when the dual clock is used. n state transition diagram 1 (dual clock) figure 3.8-2 state transition diagram 1 (dual clock) main clock mode subclock mode main sleep state main run state main stop state main clock oscillation stabilization wait subclock oscillation stabilization wait sub-run main clock oscillation stabilization wait sub-sleep state sub-stop state watch state reset state sub-run state oscillation stabilization wait reset state power-on power-on reset
81 3.8 standby mode (low power consumption) m transition and release of the clock mode (non-standby mode) table 3.8-3 transition and release of the clock mode (power-on reset is available, dual clock system) state transition transition conditions transition to the normal state (main run) in main clock mode after power-on reset [1] main clock oscillation stabilization wait time end (timebase timer output) [2] release of reset input reset in the main run state [3] external reset, software reset, or watchdog reset transition from the main run state to the sub-run state [4] sycc:scs=0 (*1) return from the sub-run state to the main run state [5] sycc:scs=1 [6] main clock oscillation stabilization wait time end (sycc: can be checked by scm) [7] external reset, software reset, or watchdog reset reset in the sub-run state [8] external reset, software reset, or watchdog reset sycc: system clock control register *1: a transition to the sub-run just after power-on occurs after the passage of the subclock oscillation stabilization wait time.
82 chapter 3 cpu m transition and release of the standby mode note: since cpu and the watchdog timer are stopped in standby mode, no software reset and watchdog reset occur. when a single clock system is used, a transition to the subclock mode is prohibited. if a transition to the subclock mode occurs, cpu stops and there is no other way to return other than resetting. table 3.8-4 transition and release of the standby mode (power-on reset is available, dual clock system) state transition transition conditions main clock mode subclock mode transition to the sleep mode [1] stbc:slp=1 <1> stbc:slp=1 release of the sleep mode [2] interrupt (various types) <2> interrupt (various types) [3] external reset <3> external reset transition to the stop mode [4] stbc:stp=1 <4> stbc:stp=1 release of the stop mode [5] external interrupt <5> external interrupt [6] main clock oscillation stabilization wait time end (timebase timer output) <6> subclock oscillation stabilization wait time end (watch prescaler output) [7] external reset <7> external reset [8] external reset (waiting for oscillation stabilization) <8> external reset (waiting for oscillation stabilization) transition to the watch mode - <9> stbc:tmd=1 (*1) release of the watch mode - <10> external interrupt or watch interrupt <11> external reset stbc: standby control register *1: a transition to the watch mode is only possible from the sub-run state (sycc: scs=0).
83 3.8 standby mode (low power consumption) 3.8.7 notes on using standby mode a transition to the standby mode does not occur even if the standby mode is set on the standby control register (stbc) when an interrupt request has arrived from a peripheral function. when returning to a normal operation state from the standby mode caused by an interrupt, operations after the return are dependent on whether or not the interrupt request is accepted. n transition to the standby mode and interrupts when an interrupt request whose interrupt priority is higher than "11" arrives at cpu from a peripheral function, a transition to the standby mode does not occur if "1" is written into the stop bit (stbc: stp), sleep bit (slp) or clock bit (tmd) of the standby control register because such write operations are ignored (no transition to the standby mode occurs even after the interrupt processing is completed). this is not related to whether the interrupt is accepted by cpu. even if cpu is processing an interrupt, a transition to the standby mode is possible if the interrupt request flag bit is cleared and there are no other interrupt requests. n release of the standby mode by an interrupt the standby mode is released if an interrupt request whose interrupt priority is higher than "11" comes from the peripheral functions in sleep mode or stop mode. this is not related to whether the interrupt is accepted by cpu. after releasing the standby mode, if the priority of the interrupt level setting register (ilr1- ilr4) corresponding to the interrupt request is higher than the interrupt level bits (ccr: il1, 0) of the condition code register and if the interrupt enable flag allows the interrupts (ccr: i=1), branching to an interrupt processing routine occurs. if the interrupt is not accepted, execution of the instruction following the instruction starting the standby mode is restarted. if no branching to an interrupt processing routine just after returning occurs, measures such as an interrupt prohibition are needed before setting the standby mode.
84 chapter 3 cpu n precaution in setting the standby mode to set the standby mode using the standby control register (stbc), follow table 3.8-5 "low power consumption settings by the standby control register (stbc)". the priority order when "1" is written into these bits is the stop mode, watch mode, and sleep mode. however, it is preferable to set "1" to one bit at a time. do not make a transition to the stop mode, sleep mode, and watch mode just after switching from the subclock mode to the main clock mode (sycc: scs=0 --> 1). make a transition to these modes after checking that the clock monitor bit (sycc: scm) of the system control register is "1". however, the content written into the clock bit (tmd) is ignored during operation in main clock mode. n oscillation stabilization wait time since the oscillator for oscillation is stopped in stop mode for both the main clock mode and subclock mode, it is necessary to take the oscillation stabilization wait time after the oscillator in each mode starts operation. as the oscillation stabilization wait time in main clock mode, take the oscillation stabilization wait time of the main clock created by the timebase timer (select one from three different kinds of wait time). as the oscillation stabilization wait time in subclock mode, take the oscillation stabilization wait time of the subclock created by the watch prescaler. in main clock mode, if the selected interval time of the timebase timer is shorter than the oscillation stabilization wait time, an interval timer interrupt request may occur during oscillation stabilization wait time. before making a transition to the stop mode in main clock mode, prohibit (tbtc: tbie=0) the interrupt request output of the timebase timer if necessary. likewise, a watch interrupt request may occur depending on the selected interval time of the watch prescaler. before making a transition to the stop mode in subclock mode, prohibit (wpcr: wie=0) the watch interrupt request output of the watch prescaler if necessary. table 3.8-5 low power consumption settings by the standby control register (stbc) stbc register mode stp (bit 7) slp (bit 6) tmd (bit 3) 000normal 001clock 010watch 100stop
85 3.9 memory access mode 3.9 memory access mode the operation mode for memory access of the mb89570 series is the single chip mode only. n single chip mode the single chip mode uses only the internal ram and rom. thus, cpu can access only the internal i/o area, ram area, and rom area (internal access). n mode pin (moda) set always "vss" to the mode pin (moda). the mode data and reset vector are read from the internal rom during reset. do not change the settings of the mode pin after the reset operation (during operation) is completed. table 3.9-1 "settings of the mode pin" lists the settings of the mode pin. n mode data set always 00 h as the mode data in the internal rom to select the single chip mode. figure 3.9-1 structure of the mode data table 3.9-1 settings of the mode pin pin state contents mpoa vss the mode data and reset vector are read from the internal rom vcc setting prohibited data 00 h except 00 h operation single chip mode selection reserved. do not set here. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address f f f d h
86 chapter 3 cpu n selection of the memory access mode only the single chip mode can be selected. table 3.9-2 "mode pins and mode data" lists the mode pins and mode data. figure 3.9-2 "memory access selection operation" shows the operation of memory access selection. figure 3.9-2 memory access selection operation table 3.9-2 mode pins and mode data memory access mode mode pin (moda) mode data single chip mode vss 00 h other modes setting prohibited setting prohibited mode pin check reset source occurred setting prohibited setting prohibited others others mode pin (moda) single chip mode mode data is read from the internal rom i/o pin, high impedance reset source release wait (external reset or oscillation stabilization wait time) reset state mode fetch mode data and reset vector fetch from the internal rom mode data check mode data single chip mode (00 h ) i/o pin function settings during program execution (run) input/output settings of each i/o pin by the port direction register (ddr) i/o pins can be used as ports
87 chapter 4 i/o port this chapter describes the functions and operations of the i/o port. 4.1 "overview of the i/o port" 4.2 "port 0" 4.3 "port 1" 4.4 "port 2" 4.5 "port 3" 4.6 "port 4" 4.7 "port 5" 4.8 "port 6" 4.9 "port 7" 4.10 "port 8" 4.11 "port 9" 4.12 "port a" 4.13 "port b" 4.14 "program example of the i/o ports"
88 chapter 4 i/o port 4.1 overview of the i/o port the i/o port can be used as 12 (82 pins) general-purpose i/o ports (parallel i/o ports). each port also serves for resources (i/o pins for various peripheral functions). n functions of the i/o port the i/o port provides the function to output data from cpu to the i/o pins and fetch the signal input into the i/o pin to send it to cpu by using the port data register (pdr). for some ports, it is possible to set the direction of i/o of the i/o pin in bit units using the port direction register (ddr). the following lists the functions of each port and the resources that each port provides. ? port 0: general-purpose i/o port ? port 1: serves as the general-purpose i/o port/resource (a/d converter pin) ? port 2: serves as the general-purpose i/o port/resource (timer output pin) ? port 3: serves as the general-purpose i/o port/resource (i 2 c/multi-address i 2 c, uaet/sio pin) ? port 4: serves as the general-purpose i/o port/resource (bridge circuit pin) ? port 5: serves as the general-purpose i/o port/resource (comparator pin) ? port 6: serves as the general-purpose i/o port/resource (lcd controller/driver segment output pin) ? port 7: serves as the general-purpose i/o port/resource (comparator pin) ? port 8: serves as the general-purpose i/o port/resource (external interrupt, a/d converter, comparator pin) ? port 9: serves as the general-purpose i/o port/resource (a/d and d/a converter pin) ? port a: serves as the general-purpose i/o port/resource (lcd controller/driver segment output pin) ? port b: serves as the general-purpose i/o port/resource (lcd controller/driver segment output pin, lcd built-in split resistance input pin)
89 4.1 overview of the i/o port table 4.1-1 "list of functions of each port" lists the functions of each port and table 4.1-2 "list of functions of each port" lists the registers of each port. table 4.1-1 list of functions of each port port name pin name input type output type function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port 0 p00 to p07 cmos cmos push-pull general- purpose i/o port p07 p06 p05 p04 p03 p02 p01 p00 port 1 p10/an4 to p17an11 general- purpose i/o port p17 p16 p15 p14 p13 p12 p11 p10 resources an11 an10 an9 an8 an7 an6 an5 an4 port 2 p20 to p27 general- purpose i/o port p27 p26 p25 p24 p23 p22 p21 p20 resources C C C C t02 C C t01 port 3 p30/scl1 to p35/u03 cmos (*1) n-ch open- drain general- purpose i/o port C C p35 p34 p33 p32 p31 p30 resources C C u03 sda2/ ui3 scl2/ uck3 alert sda1 scl1 port 4 p40/scl3/ uck1 to p43/sda4/ ui2 cmos (*2) n-ch open- drain general- purpose i/o port C C C C p43 p42 p41 p40 resources C C C C sda4/ ui2 scl4/ uck2 sda3\ui 1 scl3/ uck1 port 5 p50/alr1 to p56/ofb3 cmos cmos push-pull general- purpose i/o port C p56 p55 p54 p53 p52 p51 p50 resources C ofb3 ofb2 ofb1 ac0 alr3 alr2 alr1 port 6 p60/seg08 to p65/ seg13/u01 cmos (*3) n-ch (*3) open-drain general- purpose i/o port p65 p64 p63 p62 p61 p60 resources seg13/ u01 seg12/ u02 seg11 seg10 seg9 seg8 port 7 p70/dcin to p77/vsi3 cmos cmos push-pull general- purpose i/o port p77 p76 p75 p74 p73 p72 p71 p70 resources vsi3 vol3 vsi2 vol2 vsi1 vol1 dcin2 dcin port 8 p80/int0 to p87/an2/ sw3 cmos (*4) cmos (*5) push-pull general- purpose i/o port p87 p86 p85 p84 p83 p82 p81 p80 resources an2/ sw3 an1/ sw2 an0/ sw2 ec int3 int2 int1 int0 port 9 p90/an3 to p92/da2 cmos cmos push-pull general- purpose i/o port CCCCCp92p91p90 resourcesCCCCCda2da1an3 port a pa0/seg00 to pa7/ seg07 cmos n-ch open- drain general- purpose i/o port pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 resources seg07 seg06 seg05 seg04 seg03 seg02 seg01 seg00
90 chapter 4 i/o port port b pb0/v0 to pb7/com3 cmos (*6) n-ch open- drain general- purpose i/o port pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 resources com3 com2 com1 com0 v3 v2 v1 v0 *1: resources (uart) of p33 to p34 are hysteresis input. *2: resources become the input into the bridge circuit. resources (uart) are hysteresis input. *3: resources of p64 to p65 (uart) are the output from the bridge circuit. *4: resources of p80 to p83 (for external interrupts) are hysteresis input. *5: no output for p84 *6: pb0 to pb3 is output only. table 4.1-1 list of functions of each port (continued) port name pin name input type output type function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 4.1-2 list of registers of each port register name read/write address initial value port 0 data register (pdr0) r/w 0000 h xxxxxxxx b port 0 direction register (ddr0) w 0001 h 00000000 b port 1 data register (pdr1) r/w 0002 h xxxxxxxx b port 1 direction register (ddr1) w 0003 h 00000000 b port 2 data register (pdr2) r/w 0004 h xxxxxxxx b port 2 direction register (ddr2) r/w 0006 h 00000000 b port 3 data register (pdr3) r/w 0020 h xx111111 b port 4 data register (pdr4) r/w 0021 h xxxx1111 b port 5 data register (pdr5) r/w 0022 h xxxxxxxx b port 5 direction register (ddr5) r/w 0023 h x0000000 b port 6 data register (pdr6) r/w 0024 h xx111111 b port 7 data register (pdr7) r/w 0025 h xxxxxxxx b port 7 direction register (ddr7) r/w 0026 h 00000000 b port 8 data register (pdr8) r/w 0027 h xxxxxxxx b port 8 direction register (ddr8) r/w 0028 h 000x0000 b port 9 data register (pdr9) r/w 0029 h xxxxxxxx b port 9 direction register (ddr9) r/w 002a h xxxxx000 b port a data register (pdra) r/w 0015 h 11111111 b port b data register (pdrb) r/w 0017 h 11111111 b r/w: read/write enabled r: read only w: write only x: undefined
91 4.2 port 0 4.2 port 0 the port 0 is a general-purpose i/o port. this section describes with a particular emphasis on the functions of the general- purpose i/o port. the following shows the configuration of port 0, its pins, a pin block diagram, and related registers. n configuration of port 0 the port 0 is made up of the following three elements: m port 0 ? general-purpose i/o pin (p00 to p07) ? port 0 data register (pdr0) ? port 0 direction register (ddr0) n pins of the port 0 the port 0 has eight cmos i/o pins. table 4.2-1 "pins of port 0" lists the pins of port 0. for the circuit type, see section 1.7 "pin description". table 4.2-1 pins of port 0 port name pin name function shared resource i/o type circuit type input output port 0 p00 p00 general-purpose i/o - cmos cmos b p01 p01 general-purpose i/o - p02 p02 general-purpose i/o - p03 p03 general-purpose i/o - p04 p04 general-purpose i/o - p05 p05 general-purpose i/o - p06 p06 general-purpose i/o - p07 p07 general-purpose i/o -
92 chapter 4 i/o port n block diagram of the port 0 figure 4.2-1 block diagram of pins of port 0 note: do not use the pins to be used as analog input pins as a general-purpose port. n registers pdr0 and ddr0 of port 0 two registers pdr0 and ddr0 are available as the registers related to port 0. there is a 1:1 correspondence between the bits configuring each register and the pins of port 0. lists the correspondences between the registers and pins of port 0. pin p-ch n-ch pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) ddr internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register) table 4.2-2 correspondence between the registers and pins of port 0 port name bits of the related registers and corresponding pins port 0 pdr0, ddr0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p07 p06 p05 p04 p03 p02 p01 p00
93 4.2 port 0 4.2.1 registers of port 0 (pdr0, ddr0) this section describes the registers related to port 0. n functions of the registers of port 0 m port 0 data register (pdr0) the pdr0 register indicates the states of pins. thus, if the pins are set as output ports, the same values ("0" or "1") can be read as those of the output latch. however, if the pins set as input ports, the values of the output latch cannot be read. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m port 0 direction register (ddr0) the ddr0 register sets the i/o direction of pins for each bit. if "1" is set to a bit corresponding to a port, the port becomes an output port. if "0" is set to the bit corresponding to a port, the port becomes an input port table 4.2-3 "register functions of port 0" lists the register functions of port 0. table 4.2-3 register functions of port 0 register name data read write read/write address initial value port 0 data register (pdr0) 0 pin state is "l" "0" is set to the output latch. if port 0 operates as an output port, the "l" level is output to the pins. r/w 0000 h xxxxxxxx b 1 pin state is "h" "1" is set to the output latch. if port 0 operates as an output port, the "h" level is output to the pins. port 0 direction register (ddr0) 0 read not allowed output transistor operation is prohibited and a pin is made an input pin. w 0001 h 00000000 b 1 read not allowed output transistor operation is allowed and a pin is made an output pin r/w: read/write enabled w: write only x: undefined
94 chapter 4 i/o port 4.2.2 operation of port 0 this section describes the operations of port 0. n operation of port 0 m operation as an output port ? if "1" is set to the corresponding ddr0 register bit, the port becomes an output port. ? the operation of the output transistor is allowed when port 0 operates as an output port and data of the output latch is output to the pins. ? if data is written into the pdr0 register, the data is retained on the output latch and then output directly to the pins. ? pin values can be read by reading the pdr0 register. m operation as an input port ? if "0" is set to the corresponding ddr0 register bit, the port becomes an input port. ? the output transistor is "off" and the pins are in high impedance when port 0 operates as an input port. ? if data is written into the pdr0 register, the data is retained on the output latch but is not output to the pins. ? pin values can be read by reading the pdr0 register. m operation during a reset ? if cpu is reset, the value of the ddr0 register is initialized to "0". thus, the output transistor is turned "off" (input port) and the pins are put into high impedance. ? the pdr0 register is not initialized by a reset. thus, if port 0 is used as an output port, it is necessary to set output data to the pdr0 register and then set output to the corresponding ddr0 register. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, prohibition of the port input is forced regardless of the value of the ddr0 register and the pins are put into high impedance. the input is fixed to prevent leakage due to input opening.
95 4.2 port 0 table 4.2-4 "pin states of port 0" lists the pin states of port 0. table 4.2-4 pin states of port 0 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p00 to p07 general-purpose i/o port hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
96 chapter 4 i/o port 4.3 port 1 the port 1 is a general-purpose i/o port. this section describes the functions of the general-purpose i/o port. the following shows the configuration of port 1, its pins, a pin block diagram, and related registers. n configuration of port 1 the port 1 is made up of the following three elements: ? general-purpose i/o pin/analog input pin (p10/an5 to p17/an12) ? port 1 data register (pdr1) ? port 1 direction register (ddr1) n pins of port 1 the port 1 has eight cmos i/o pins. if these pins are used as analog input pins by the a/d converter, do not use them as a general- purpose i/o port. table 4.3-1 "pins of port 1" lists the pins of port 1. for the circuit type, see section 1.7 "pin description". table 4.3-1 pins of port 1 port name pin name function shared resource i/o type circuit type input output port 1 p10/an4 p10 general-purpose i/o analog input analog /cmos cmos e p11/an5 p11 general-purpose i/o analog input p12/an6 p12 general-purpose i/o analog input p13/an7 p13 general-purpose i/o analog input p14/an8 p14 general-purpose i/o analog input p15/an9 p15 general-purpose i/o analog input p16/an10 p16 general-purpose i/o analog input p17/an11 p17 general-purpose i/o analog input
97 4.3 port 1 n block diagram of port 1 figure 4.3-1 block diagram of the pins of port 1 n registers of port 1 two registers pdr1 and ddr1 are available as registers related to port 1. there is a 1:1 correspondence between the bits configuring each register and pins of port 1. table 4.3-2 "correspondence between the registers and pins of port 1" lists the correspondences between the registers and pins of port 1. pin p-ch n-ch pdr read pdr write ddr write ddr a/d input enable bit a/d converter channel select bit to a/d converter analog input internal data bus pdr (port data register) output latch (port direction register) ddr (port direction register) stop/watch mode (spl=1) pdr read (for bit manipulation instructions) spl: pin state designate bit of the standby control register (stbc) stop/watch mode table 4.3-2 correspondence between the registers and pins of port 1 port name bits of the related registers and corresponding pins port 1 pdr1, ddr1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p17 p16 p15 p14 p13 p12 p11 p10
98 chapter 4 i/o port 4.3.1 registers of the port 1 (pdr1, ddr1) this section describes the registers related to port 1. n functions of the registers of port 1 m port 1 data register (pdr1) the pdr1 register indicates the states of pins. thus, if the pins are set as output ports, the same values ("0" or "1") can be read as those of the output latch. however, if the pins are set as input ports, the values of the output latch cannot be read. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m port 1 direction register (ddr1) the ddr1 register sets the i/o direction of pins for each bit. if "1" is set to the bit corresponding to a port, the port becomes an output port. if "0" is set to the bit corresponding to a port, the port becomes an input port. table 4.3-3 "register functions of port 1" lists the register functions of port 1. table 4.3-3 register functions of port 1 register name data read write read/write address initial value port 1 data register (pdr1) 0 pin state is "l" "0" is set to the output latch. if port 1 operates as an output port, the "l" level is output to the pins. r/w 0002 h xxxxxxxx b 1 pin state is "h" "1" is set to the output latch. if port 1 operates as an output port, the "h" level is output to the pins. port 1 direction register (ddr1) 0 read not allowed output transistor operation is prohibited and a pin is made an input pin (analog input enabled). w 0003 h 00000000 b 1 read not allowed output transistor operation is allowed and a pin is made an output pin. r/w: read/write enabled w: write only x: undefined
99 4.3 port 1 n register related to port 1 m a/d port input enable register (aden2) 002e h to use port 1 for analog input, set "1" to the bit corresponding to the aden2 register to help prevent the dc pass when an intermediate level is entered. note: to use the port 1 for port input, "0" must be set to the input enable bit of the aden2 register.
100 chapter 4 i/o port 4.3.2 operation of the port 1 this section describes the operations of port 1. n operation of port 1 m operation as an output port ? if "1" is set to the corresponding ddr1 register bit, the port becomes an output port. ? the operation of the output transistor is allowed when port 1 operates as an output port and data of the output latch is output to the pins. ? if data is written into the pdr1 register, the data is retained on the output latch and then output directly to the pins. ? pin values can be read by reading the pdr1 register. m operation as an input port ? if "0" is set to the corresponding ddr1 register bit, the port becomes an input port. ? the output transistor is "off" and the pins are in high impedance when port 1 operates as an input port. ? if data is written into the pdr1 register, the data is retained on the output latch but is not output to the pins. ? pin values can be read by reading the pdr1 register. m operation for analog input ? to use port 1 for analog input, write "0" into the bit of the ddr1 register corresponding to the analog input pin or "1" into the corresponding bit of the aden2 register. m operation during a reset ? if cpu is reset, the value of the ddr1 register is initialized to "0". thus, the output transistor is turned "off" (input port) and the pins are put into high impedance. ? the pdr1 register is not initialized by a reset. thus, if port 1 is used as an output port, it is necessary to set output data to the pdr1 register and then set output to the corresponding ddr1 register. ? the aden2 register is initialized "1" by a reset. thus, if port 1 is used for port input, "0" must be set to the corresponding bit of the aden2 register. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, prohibition of the port input is effected regardless of the value of the ddr1 register and the pins are put into high impedance. the input is fixed to prevent leakage due to input opening.
101 4.3 port 1 table 4.3-4 "pin states of port 1" lists the pin states of port 1. table 4.3-4 pin states of port 1 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p10/an4 to p17/an11 general-purpose i/o port/analog input hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
102 chapter 4 i/o port 4.4 port 2 the port 2 is a general-purpose i/o port. this section describes the functions of the general-purpose i/o port. the following shows the configuration of port 2, its pins, a pin block diagram, and related registers. n configuration of port 2 the port 2 is made up of the following three elements: ? general-purpose i/o pin (p20/t01 to p27) ? port 2 data register (pdr2) ? port 2 direction register (ddr2) n pins of the port 2 port 2 has eight cmos i/o pins. of these pins, if resources are used by the pins also serving for resources, do not use as a general-purpose i/o port. table 4.4-1 "pins of port 2" lists the pins of port 2. for the circuit type, see section 1.7 "pin description". table 4.4-1 pins of port 2 port name pin name function shared resource i/o type circuit type input output port 2 p20/t01 p20 general-purpose i/o 8/16-bit timer/counter, timer 1 output cmos cmos b p21 p21 general-purpose i/o C p22 p22 general-purpose i/o C p23/t02 p23 general-purpose i/o 8/16-bit timer/counter, timer 2 output p24 p24 general-purpose i/o C p25 p25 general-purpose i/o C p26 p26 general-purpose i/o C p27 p27 general-purpose i/o C
103 4.4 port 2 n block diagram of port 2 figure 4.4-1 block diagram of pins of port 2 n registers of the port 2 two registers pdr2 and ddr2 are available as the registers related to port 2. there is a 1:1 correspondence between the bits configuring each register and the pins of port 2. table 4.4-2 "correspondence between the registers and pins of port 2" lists the correspondence between the registers and pins of port 2. pin p-ch n-ch from resource output from resource output enable ddr ddr read p20/p23 only pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register) table 4.4-2 correspondence between the registers and pins of port 2 port name bits of the related registers and corresponding pins port 2 pdr2, ddr2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p27 p26 p25 p24 p23 p22 p21 p20
104 chapter 4 i/o port 4.4.1 registers of port 2 (pdr2, ddr2) this section describes the registers related to port 2. n functions of the registers of port 2 m port 2 data register (pdr2) the pdr2 register indicates the states of pins. thus, if the pins are set as output ports, the same values ("0" or "1") can be read as those of the output latch. however, if the pins set as input ports, the values of the output latch cannot be read. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m port 2 direction register (ddr2) the ddr2 register sets the i/o direction of pins for each bit. if "1" is set to the bit corresponding to a port, the port becomes an output port. if "0" is set to the bit corresponding to a port, the port becomes an input port m settings for resource output to use a resource, set the operation enable bit of the resource. since the resource output takes precedence, settings of the pdr2 and ddr2 registers corresponding to the resource output pins have no significance regardless of the output value and output permission of the resource.
105 4.4 port 2 table 4.4-3 "register functions of port 2" lists the register functions of port 2. table 4.4-3 register functions of port 2 register name data read write read/write address initial value port 2 data register (pdr2) 0 pin state is "l" "0" is set to the output latch. if port 2 operates as an output port, the "l" level is output to the pins. r/w 0004 h xxxxxxxx b 1 pin state is "h" "1" is set to the output latch. if port 2 operates as an output port, the "h" level is output to the pins. port 2 direction register (ddr2) 0 input port state output transistor operation is prohibited and a pin is made an input pin. r/w 0006 h 00000000 b 1 output port state output transistor operation is allowed and a pin is made an output pin. r/w: read/write enabled x: undefined
106 chapter 4 i/o port 4.4.2 operation of port 2 this section describes the operations of port 2. n operation of port 2 m operation as an output port ? if "1" is set to the corresponding ddr2 register bit, the port becomes an output port. ? the operation of the output transistor is allowed when port 2 operates as an output port and data of the output latch is output to the pins. ? if data is written into the pdr2 register, the data is retained on the output latch and then output directly to the pins. ? pin values can be read by reading the pdr2 register. m operation as an input port ? if "0" is set to the corresponding ddr2 register bit, the port becomes an input port. ? the output transistor is "off" and the pins are in high impedance when port 2 operates as an input port. ? if data is written into the pdr2 register, the data is retained on the output latch but is not output to the pins. ? pin values can be read by reading the pdr2 register. m operation during resource output ? if the operation enable bit of a resource is set, the corresponding pin is made ready for resource output. ? because the pin values can be read through the pdr2 register even when a resource is allowed, output values of the resource can be read. m operation during a reset ? if cpu is reset, the value of the ddr2 register is initialized to "0". thus, the output transistor is turned "off" (input port) and the pins are put into high impedance. ? the pdr2 register is not initialized by a reset. thus, if port 2 is used as an output port, it is necessary to set output data to the pdr2 register and then set output to the corresponding ddr2 register. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, prohibition of the port input is forced regardless of the value of the ddr2 register and the pins are put into high impedance. the input is fixed to prevent leakage due to input opening.
107 4.4 port 2 table 4.4-4 "pin states of port 2" lists the pin states of port 2. table 4.4-4 pin states of port 2 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p20 to p27 general-purpose i/o port hi-z (*1) hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance *1: note that p20 and p23 will not be in high impedance even if (stbc=spl) is set to "1".
108 chapter 4 i/o port 4.5 port 3 the port 3 is a general-purpose i/o port. each pin can be used by switching between the resource and port in bit units. this section describes the functions of the general- purpose i/o port. the following shows the configuration of port 3, its pins, pin block diagrams, and the related register. n configuration of port 3 port 3 is made up of the following two elements: ? general-purpose i/o pin/resource i/o pin (p30/scl1 to p35/u03) ? port 3 data register (pdr3) n pins of the port 3 port 3 has six cmos input/n-ch open-drain output i/o pins. table 4.5-1 "pins of port 3" lists the pins of port 3. for the circuit type, see section 1.7 "pin description". table 4.5-1 pins of port 3 port name pin name function shared resource i/o type circuit type input output port 3 p30 general-purpose i/o scl1 multi-address i 2 c cmos n-ch open- drain f p31 general-purpose i/o sda1 multi-address i 2 c p32 general-purpose i/o alert multi-address i 2 ch p33 general-purpose i/o scl2/uck3 i 2 c/uart g p34 general-purpose i/o sda2/ui3 i 2 c/uart p35 general-purpose i/o u03 uart h
109 4.5 port 3 n block diagram of port 3 figure 4.5-1 block diagram of pins of port 3 (p30, p31) figure 4.5-2 block diagram of pins of port 3 (p33, p34) pin resource output from resource enable bit resource input output tr. from bridge circuits pin pdr read pdr read (for bit manipulation instructions) pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus stop/watch mode stop/watch mode spl: pin state designate bit of the standby control register (stbc) pdr read i 2 c output multi-address i 2 c output i 2 c input from bridge circuits from bridge circuits from bridge circuits multi-address i 2 c input from bridge circuits output tr. uart input uart output (p33 only) pin pin pdr read (for bit manipulation instructions) pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus stop/watch mode stop/watch mode stop/watch mode spl: pin state designate bit of the standby control register (stbc)
110 chapter 4 i/o port figure 4.5-3 block diagram of pins of port 3 (p32, p35) n register of port 3 one register pdr3 is available as the register related to port 3. there is a 1:1 correspondence between the bits configuring the pdr3 register and the pins of port 3. table 4.5-2 "correspondence between the registers and pins of port 3" lists the correspondence between the register and pins of port 3. output tr. (alert output) uart output (from malr: aen bit of multi-address i 2 c) from bridge circuits internal data bus pdr (port data register) pdr read (for bit manipulation instructions) output latch pdr write pdr read spl: pin state designate bit of the standby control register (stbc) stop/watch mode (spl=1) stop/watch mode pin table 4.5-2 correspondence between the registers and pins of port 3 port name bits of the related registers and corresponding pins port 3 pdr3 C C bit 5bit 4bit 3bit 2bit 1bit 0 corresponding pin C C p35 p34 p33 p32 p31 p30
111 4.5 port 3 4.5.1 register of port 3 (pdr3) this section describes the register related to port 3. n functions of the register of port 3 m port 3 data register (pdr3) the pdr3 register sets the states of pins. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. table 4.5-3 "register functions of port 3" lists the register functions of port 3. n registers related to port 3 m bridge circuit select register 2 (brsr2) 005d h , bridge circuit select register 3 (brsr3) 0019 h if port 3 is used as a general-purpose port, select the port function by using the brsr2/ brsr3 registers. table 4.5-3 register functions of port 3 register name data read write read/write address initial value port 3 data register (pdr3) 0 pin state is "l" the "l" level is output to the pins ("0" is set to the output latch and the output transistor is turned "on"). r/w 0020 h xx111111 b 1 pin state is "hi-z" pins are raised to hi-z ("1" is set to the output latch and the output transistor is turned "off"). r/w: read/write enabled x: undefined hi-z: high impedance
112 chapter 4 i/o port 4.5.2 operation of port 3 this section describes the operations of port 3. n operation of port 3 m operation as an output port ? if data is written into the pdr3 register, data is retained on the output latch. if the value of the output latch is "0", the output transistor is turned "on" and the "l" level is output to the pins. if the value of the output latch is "1", the output transistor is turned "off" and the pins are put into high impedance. when the output pins are pulled up, the port is pulled up if the value of the output latch is "1". m operation as an input port ? pin values can be read by reading the pdr3 register. m operation during a reset ? if cpu is reset, the value of the pdr3 register is initialized to "1". thus, all output transistors are turned "off" and the pins are put into in high impedance. m operation during resource output ? to use resources, set the output enable bit of each resource. since the resource output takes precedence, settings of the pdr3 register corresponding to the resource output pins have no significance. m operation in stop mode and watch mode if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, the output transistor is forced "off" and the pins are put into high impedance. the input is fixed to prevent leakage due to input opening. table 4.5-4 "pin states of port 3" lists the pin states of port 3. table 4.5-4 pin states of port 3 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p30 to p35 general-purpose i/o port/ resource i/o hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
113 4.6 port 4 4.6 port 4 port 4 is a general-purpose i/o port. each pin can be used by switching between the resource and port in units of bits. this section describes the functions of the general- purpose i/o port. the following shows the configuration of port 4, its pins, a pin block diagram, and the related register. n configuration of port 4 port 4 is made up of the following two elements: ? general-purpose i/o pin/resource i/o pin (p40/scl3 to p43/sda4) ? port 4 data register (pdr4) n pins of the port 4 port 4 has four cmos input/n-ch open-drain output i/o pins. table 4.6-1 "pins of port 4" lists the pins of port 4. for the circuit type, see section 1.7 "pin description". table 4.6-1 pins of port 4 port name pin name function shared resource i/o type circuit type input output port 4 p40 general-purpose i/o scl3/uck1 bridge circuit cmos n-ch open- drain g p41 general-purpose i/o sda3/ui1 bridge circuit p42 general-purpose i/o scl4/uck2 bridge circuit p43 general-purpose i/o sda4/ui2 bridge circuit
114 chapter 4 i/o port n block diagram of port 4 figure 4.6-1 block diagram of pins of port 4 n register of the port 4 one register pdr4 is available as the register related to port 4. there is a 1:1 correspondence between the bits configuring the pdr4 register and the pins of port 4. table 4.6-2 "correspondence between the register and pins of port 4" lists the correspondences between the register and pins of port 4. pin pin pdr read i 2 c output multi-address i 2 c output i 2 c input from bridge circuits from bridge circuits from bridge circuits multi-address i 2 c input from bridge circuits output tr. uart input uart output (p40 and p42 only) internal data bus pdr (port data register) pdr read(for bit manipulation instructions) pdr write output latch stop/watch mode (spl=1) stop/watch mode stop/watch mode stop/watch mode spl: pin state designate bit of the standby control register (stbc) table 4.6-2 correspondence between the register and pins of port 4 port name bits of the related registers and corresponding pins port 4 pdr4 CCCCbit 3bit 2bit 1bit 0 corresponding pinCCCCp43p42p41p40
115 4.6 port 4 4.6.1 register of port 4 (pdr4) this section describes the register related to port 4. n functions of the register of port 4 m port 4 data register (pdr4) the pdr4 register sets the states of pins. since the values of the output latch instead of the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. table 4.6-3 "register functions of port 4" lists the register functions of port 4. n registers related to port 4 m bridge circuit select register 2 (brsr2) 005d h , bridge circuit select register 3 (brsr3) 0019 h if port 4 is used as a general-purpose port, select the port function by using the brsr2/ brsr3 registers. table 4.6-3 register functions of port 4 register name data read write read/write address initial value port 4 data register (pdr4) 0 pin state is "l" the "l" level is output to the pins ("0" is set to the output latch and the output transistor is turned "on"). r/w 0021 h xxxx1111 b 1 pin state is "hi-z" pins are raised to hi-z ("1" is set to the output latch and the output transistor is turned "off"). r/w: read/write enabled x: undefined hi-z: high impedance
116 chapter 4 i/o port 4.6.2 operation of port 4 this section describes the operations of port 4. n operation of port 4 m operation as an output port ? if data is written into the pdr4 register, the data is retained on the output latch. if the value of the output latch is "0", the output transistor is turned "on" and the "l" level is output to the pins. if the value of the output latch is "1", the output transistor is turned "off" and the pins are put into high impedance. when the output pins are pulled up, the port is pulled up if the value of the output latch is "1". m operation as an input port ? pin values can be read by reading the pdr4 register. m operation during a reset ? if cpu is reset, the value of the pdr4 register is initialized to "1". thus, all output transistors are turned "off" and the pins are put into in high impedance. m operation during resource output ? to use resources, set the output enable bit of each resource. since the resource output takes precedence, settings of the pdr4 register corresponding to the resource output pins have no significance. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, the output transistor is forced "off" and the pins are put into high impedance. the input is fixed to prevent leakage due to input opening. table 4.6-4 "pin states of port 4" lists the pin states of port 4. table 4.6-4 pin states of port 4 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p40 to p43 general-purpose i/o port/ resource i/o hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
117 4.7 port 5 4.7 port 5 port 5 is a general-purpose i/o port which also serves as a resource output. each pin can be used by switching between the resource and the port in units of bits. this section describes the functions of the general-purpose i/o port. the following shows the configuration of port 5, its pins, a pin block diagram, and the related register. n configuration of port 5 port 5 is made up of the following three elements: ? general-purpose i/o pin/resource i/o pin (p50/alr1 to p56/ofb3) ? port 5 data register (pdr5) ? port 5 direction register (ddr5) n pins of port 5 port 5 has seven cmos i/o pins. of these pins, if resources are used by the pins which also serve as resources, do not use them as a general-purpose i/o port. table 4.7-1 "pins of port 5" lists the pins of port 5. for the circuit type, see section 1.7 "pin description". table 4.7-1 pins of port 5 port name pin name function shared resource i/o type circuit type input output port 5 p50/alr1 p50 general-purpose i/o alr1 comparator output cmos cmos b p51/alr2 p51 general-purpose i/o alr2 comparator output p52/alr3 p52 general-purpose i/o alr3 comparator output p53/ac0 p53 general-purpose i/o ac0 comparator output p54/ofb1 p54 general-purpose i/o ofb1 comparator output p55/ofb2 p55 general-purpose i/o ofb2 comparator output p56/ofb3 p56 general-purpose i/o ofb3 comparator output
118 chapter 4 i/o port n block diagram of port 5 figure 4.7-1 block diagram of pins of port 5 n registers of port 5 two registers pdr5 and ddr5 are available as the registers related to port 5. there is a 1:1 correspondence between the bits configuring each register and the pins of port 5. table 4.7-2 "correspondence between the register and pins of port 5" lists the correspondences between the registers and pins of port 5. p-ch n-ch from resource output from resource output enable ddr ddr read internal data bus pin pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register) table 4.7-2 correspondence between the register and pins of port 5 port name bits of the related registers and corresponding pins port 5 pdr5, ddr5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin C p56 p55 p54 p53 p52 p51 p50
119 4.7 port 5 4.7.1 registers of the port 5 (pdr5, ddr5) this section describes the registers related to port 5. n functions of the registers of port 5 m port 5 data register (pdr5) the pdr5 register indicates the states of pins. thus, if the pins are set as output ports, the same values ("0" or "1") can be read as those of the output latch. however, if the pins set as input ports, values of the output latch cannot be read. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m port 5 direction register (ddr5) the ddr5 register sets the i/o direction of pins for each bit. if "1" is set to the bit corresponding to a port, the port becomes an output port. if "0" is set to the bit corresponding to a port, the port becomes an input port m settings for resource output to use a resource, set the operation enable bit of the resource. since the resource output takes precedence, settings of the pdr5 and ddr5 registers corresponding to the resource output pins have no significance regardless of the output value and output permission of the resource.
120 chapter 4 i/o port table 4.7-3 "register functions of port 5" lists the register functions of port 5. table 4.7-3 register functions of port 5 register name data read write read/write address initial value port 5 data register (pdr5) 0 pin state is "l" "0" is set to the output latch. if port 5 operates as an output port, the "l" level is output to the pins. r/w 0022 h xxxxxxxx b 1 pin state is "h" "1" is set to the output latch. if port 5 operates as an output port, the "h" level is output to the pins. port 5 direction register (ddr5) 0 input port state output transistor operation is prohibited and a pin is made an input pin. r/w 0023 h x0000000 b 1 output port state output transistor operation is allowed and a pin is made an output pin. r/w: read/write enabled x: undefined
121 4.7 port 5 4.7.2 operation of port 5 this section describes the operations of port 5. n operation of port 5 m operation as an output port ? if "1" is set to the corresponding ddr5 register bit, the port becomes an output port. ? the operation of the output transistor is allowed when port 5 operates as an output port and data of the output latch is output to the pins. ? if data is written into the pdr5 register, the data is retained on the output latch and then output directly to the pins. ? pin values can be read by reading the pdr5 register. m operation as an input port ? if "0" is set to the corresponding ddr5 register bit, the port becomes an input port. ? the output transistor is "off" and the pins are in high impedance when port 5 operates as an input port. ? if data is written into the pdr5 register, the data is retained on the output latch but is not output to the pins. ? pin values can be read by reading the pdr5 register. m operation during resource output ? if the operation enable bit of a resource is set, the corresponding pin becomes ready for resource output. since the resource output takes precedence, settings of the ddr5 register corresponding to the resource output pins have no significance. ? because the pin values can be read through the pdr5 register even when resource output is allowed, output values of the resource can be read. m operation during a reset ? if cpu is reset, the bit values of the ddr5 register are initialized to "0". thus, the output transistor is turned "off" (input port) and the pins are put into high impedance. ? the bits of the pdr5 register are not initialized by a reset. thus, if port 5 is used as an output port, it is necessary to set output data to the pdr5 register and then set output to the corresponding ddr5 register. m operation in stop mode and watch mode if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, the pins are put into high impedance because the output transistor is forced "off" regardless of the value of the ddr5 register. the input is fixed to prevent leakage due to input opening.
122 chapter 4 i/o port table 4.7-4 "pin states of port 5" lists the pin states of port 5. table 4.7-4 pin states of port 5 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p50 to p56 general-purpose i/o port/ resource i/o hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
123 4.8 port 6 4.8 port 6 port 6 is a general-purpose i/o port which also serves for lcd controller/driver segment output. the i/o port and lcd controller/driver segment output can be selected by the register setting. this section describes with a particular emphasis on the functions of the general-purpose i/o port. the following shows the configuration of port 6, its pins, a pin block diagram, and the related register. n configuration of port 6 port 6 is made up of the following two elements: m port 6 ? general-purpose i/o pin/resource output (p60/seg08 to p65/seg13/u01) ? port 6 data register (pdr6) n pins of port 6 port 6 has six n-ch open-drain output i/o pins. if the resource output pins are selected, do not use them as a general-purpose port. table 4.8-1 "pins of port 6" lists the pins of port 6. for the circuit type, see section 1.7 "pin description". table 4.8-1 pins of port 6 port name pin name function shared resource i/o type circuit type input output port 6 p60/seg08 p60 general-purpose i/o seg08 lcd controller/driver segment output cmos n-ch open- drain j to to to p63/seg11 p63 general-purpose i/o seg11 lcd controller/driver segment output p64/seg12/ u02 p64 general-purpose i/o seg12 lcd controller/driver segment output/u02 output p65/seg13/ u01 p65 general-purpose i/o seg13 lcd controller/driver segment output/u01 output
124 chapter 4 i/o port n block diagram of port 6 figure 4.8-1 block diagram of the pins of port 6 note: do not set pdr=0 for pins to be used as lcd controller/driver segment. n register of port 6 one register pdr6 is available as the register related to port 6. there is a 1:1 correspondence between the bits configuring the register pdr6 and the pins of port 6. table 4.8-2 "correspondence between the register and pins of port 6" lists the correspondences between the register and pins of port 6. nch from resource output enable bit from resource output uart output bux of bridge circuits p64 and p65 only pin pdr read pdr read (for bit manipulation instructions) pdr write output latch stop/watch mode (spl=1) pdr (port data register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) internal data bus table 4.8-2 correspondence between the register and pins of port 6 port name bits of the related registers and corresponding pins port 6 pdr6 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 corresponding pin C C p65 p64 p63 p62 p61 p60
125 4.8 port 6 4.8.1 register the port 6 (pdr6) this section describes the register related to port 6. n functions of the register of port 6 m port 6 data register (pdr6) the pdr6 register sets the states of pins. since the values of the output latch instead of the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m settings for resource output to use port with the setting for resource output, set "1" to pdr of the pin to be used so that the resource output is not affected. table 4.8-3 "register functions of port 6" lists the register functions of port 6. table 4.8-3 register functions of port 6 register name data read write read/write address initial value port 6 data register (pdr6) 0 pin state is "l" "0" is set to the output latch and the "l" level is output to the pins. r/w 0024 h xx111111 b 1 pin state is "h" "1" is set to the output latch and the "hi-z" level is output to the pins. r/w: read/write enabled x: undefined hi-z: high impedance
126 chapter 4 i/o port n registers related to port 6 m lcd controller/driver control register 2 (lcr2) 005f h to use the port 6 for lcd controller/driver output, set "1" to the corresponding bit of the lcr2 register. note: to use the port 6 as a port, it is necessary to set "0" to the selection bit of the lcr2 register. m bridge circuit select register 3 (brsr3) 0019 h to use p64 and p65 for uart output, enable the serial data output (smc2: txoe=1) and then select the uart function through the brsr3 register.
127 4.8 port 6 4.8.2 operation of port 6 this section describes the operations of port 5. n operation of port 6 m operation as an output port ? if data is written into the pdr6 register, the data is retained on the output latch and then output directly to the pins. ? when using port 6 as an output port, it cannot be used for lcd controller/driver segment output. m operation during lcd controller/driver segment output ? set "1" to the bit of the pdr6 register corresponding to the lcd controller/driver segment output pin to put the output transistor into high impedance (prohibit uart output for p64 and p65). m operation as an input port ? pin values can be read by reading the pdr6 register (when the lcd controller/driver segment output is not selected). m operation during a reset ? if cpu is reset, the value of the pdr6 register is initialized to "1". thus, all output transistors are turned "off" (input port) and the pins are put into high impedance. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, the pins are put into high impedance. the input is fixed to prevent leakage due to input opening. table 4.8-4 "pin states of port 6" lists the pin states of port 6. table 4.8-4 pin states of port 6 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p60 to p65 general-purpose i/o port/lcd controller/driver segment output/ uart output hi-z (*1) hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance *1: the previous state is retained during lcd controller/driver segment output.
128 chapter 4 i/o port 4.9 port 7 port 7 is a general-purpose i/o port which also serves as a resource input. this section describes with a particular emphasis on the functions of the general- purpose i/o port. the following shows the configuration of port 7, its pins, a pin block diagram, and the related register. n configuration of port 7 port 7 is made up of the following three elements: m port 7 ? general-purpose i/o pin/resource output (p70/dcin to p76/vsi3) ? port 7 data register (pdr7) ? port 7 direction register (ddr7) n pins of port 7 port 7 has eight cmos i/o pins. if these pins are used as a comparator input pin, do not use them as a general-purpose i/o port. table 4.9-1 "pins of port 7" lists the pins of port 7. for the circuit type, see section 1.7 "pin description". table 4.9-1 pins of port 7 port name pin name function shared resource i/o type circuit type input output port 7 p70/ dcin p70 general-purpose i/o comparator input comparator/ cmos cmos n p71/ dcin2 p71 general-purpose i/o comparator input p72/ vol1 p72 general-purpose i/o comparator input p73/vsi1 p73 general-purpose i/o comparator input p74/ vol2 p74 general-purpose i/o comparator input p75/vsi2 p75 general-purpose i/o comparator input p76/ vol3 p76 general-purpose i/o comparator input p77/vsi3 p77 general-purpose i/o comparator input
129 4.9 port 7 n block diagram of port 7 figure 4.9-1 block diagram of pins of port 7 note: do not use the pins to be used as a comparator input pin as a general-purpose port. n registers pdr7 and ddr7 of port 7 two registers pdr7 and ddr7 are available as the registers related to port 7. there is a 1:1 correspondence between the bits configuring each register and the pins of port 7. table 4.9-2 "correspondence between the registers and pins of port 7" lists the correspondence between the registers and pins of port 7. p-ch n-ch ddr comparator input control bit comparator comparator operation enable bit pin pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register) table 4.9-2 correspondence between the registers and pins of port 7 port name bits of the related registers and corresponding pins port 7 pdr7, ddr7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pin p77 p76 p75 p74 p73 p72 p71 p70
130 chapter 4 i/o port 4.9.1 registers of port 7 (pdr7, ddr7) this section describes the registers related to port 7. n functions of the registers of port 7 m port 7 data register (pdr7) the pdr7 register indicates the states of pins. thus, if the pins are set as output ports, the same values ("0" or "1") can be read as those of the output latch. however, if the pins are set as input ports, the values of the output latch cannot be read. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m port 7 direction register (ddr7) the ddr7 register sets the i/o direction of pins for each bit. if "1" is set to the bit corresponding to a port, the port becomes an output port. if "0" is set to the bit corresponding to a port, the port becomes an input port. m settings for resource input to use port 7 for resource input, set "0" to the bit of the ddr7 register corresponding to the resource input pin and set "1" to the bit corresponding to the cier register. table 4.9-3 "register functions of port 7" lists the register functions of port 7. table 4.9-3 register functions of port 7 register name data read write read/write address initial value port 7 data register (pdr7) 0 pin state is "l" the "l" level is output to the pins if port 7 operates as an output port. r/w 0025 h xxxxxxxx b 1 pin state is "h" the "h" level is output to the pins if port 7 operates as an output port. port 7 direction register (ddr7) 0 input port state output transistor operation is prohibited and a pin is made an input pin. r/w 0026 h 00000000 b 1 output port state output transistor operation is allowed and a pin is made an output pin. r/w: read/write enabled x: undefined
131 4.9 port 7 n register related to port 7 m comparator input enable register (cier) 0059h to use port 7 for comparator input and to help prevent the dc pass when an intermediate level is entered, set "1" to the corresponding bit of the cier3 register. note: to use port 7 for port input, "0" must be set to the input enable bit of the cosr3 register.
132 chapter 4 i/o port 4.9.2 operation of port 7 this section describes the operations of port 7. n operation of port 7 m operation as an output port ? if "1" is set to the corresponding ddr7 register bit, the port becomes an output port. ? the operation of the output transistor is allowed when port 7 operates as an output port and data of the output latch is output to the pins. ? if data is written into the pdr7 register, the data is retained on the output latch and then output directly to the pins. ? pin values can be read by reading the pdr7 register. m operation as an input port ? if "0" is set to the corresponding ddr7 register bit, the port becomes an input port. ? the output transistor is "off" and the pins are in high impedance when port 7 operates as an input port. ? if data is written into the pdr7 register, the data is retained on the output latch but is not output to the pins. ? pin values can be read by reading the pdr7 register. m operation during comparator input ? set the operation enable bit of the comparator to use port 7 for comparator input. m operation during a reset ? if cpu is reset, the value of the ddr7 register is initialized to "0". thus, the output transistor is turned "off" (input port) and the pins are put into high impedance. ? the pdr7 register is not initialized by a reset. thus, to use port 7 as an output port, data must be output to the pdr7 register and the output must be set to the corresponding ddr7 register. ? the cier register is initialized to "1" by a reset. thus, to use port 7 for port input, "0" must be set to the corresponding bit of the cier register. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, prohibition of the port input occurs regardless of the value of the ddr7 register and the pins are put into high impedance. the input is fixed to prevent leakage due to input opening.
133 4.9 port 7 table 4.9-4 "pin states of port 7" lists the pin states of port 7. table 4.9-4 pin states of port 7 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p70 to p77 general-purpose i/o port/ comparator input hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
134 chapter 4 i/o port 4.10 port 8 the port 8 is a general-purpose i/o port which also serves as a resource input. each pin can be used by switching between the resource and the port in units of bits. this section describes the functions of the general-purpose i/o port. the following shows the configuration of port 8, its pins, pin block diagrams, and the related register. n configuration of port 8 port 8 is made up of the following three elements: ? general-purpose i/o pin/resource input pin (p80/int0 to p87/an2/sw3) ? port 8 data register (pdr8) ? port 8 direction register (ddr8) n pins of port 8 port 8 has eight cmos i/o pins. of these pins, if resources are used by the pins which also serve as resources, do not use them as a general-purpose i/o port. table 4.10-1 "ins of port 8" lists the pins of port 8. table 4.10-1 pins of port 8 port name pin name function shared resource i/o type circuit type input output port 8 p80/int0 p80 general-purpose i/o int0 external interrupt cmos (*1) cmos k p81/int1 p81 general-purpose i/o int1 external interrupt p82/int2 p82 general-purpose i/o int2 external interrupt p83/int3 p83 general-purpose i/o int3 external interrupt p84/ p84 general-purpose input C cmos Co p85/an0/ sw1 p85 general-purpose i/o an0 analog input sw1 comparator input cmos l p86/an1/ sw2 p86 general-purpose i/o an1 analog input sw2 comparator input p87/an2/ sw3 p87 general-purpose i/o an2 analog input sw3 comparator input *1: the resource is hysteresis. for the circuit type, see section 1.7 "pin description".
135 4.10 port 8 figure 4.10-1 block diagram of pins of port 8 (p84) n block diagram of port 8 figure 4.10-2 block diagram of pins of port 8 (p80 to p83) to ec input pin pdr read pdr (port data register) internal data bus p-ch n-ch ddr edge select bit to external interrupt circuits pin pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register)
136 chapter 4 i/o port figure 4.10-3 block diagram of pins of port 8 (p85 to p87) n registers of port 8 two registers pdr8 and ddr8 are available as the registers related to port 8. there is a 1:1 correspondence between the bits configuring each register and the pins of port 8. table 4.10-2 "correspondence between the registers and pins of port 8" lists the correspondences between the registers and pins of port 8. p-ch n-ch ddr a/d input enable bit a/d converter channel select bit to a/d converter analog input comparator input control bit comparator operation enable bit comparator pin pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register) table 4.10-2 correspondence between the registers and pins of port 8 port name bits of the related registers and corresponding pins port 8 pdr8, ddr8 bit 7 bit 6 bit 5 bit 4 (*1) bit 3bit 2bit 1bit 0 corresponding pin p87 p86 p85 p84 p83 p82 p81 p80 *1: bit4 of ddr8 does not correspond to p84.
137 4.10 port 8 4.10.1 registers of port 8 (pdr8, ddr8) this section describes the registers related to port 8. n functions of the registers of port 8 m port 8 data register (pdr8) the pdr8 register indicates the states of pins. thus, if the pins are set as output ports, the same values ("0" or "1") can be read as those of the output latch. however, if the pins are set as input ports, the values of the output latch cannot be read. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m port 8 direction register (ddr8) the ddr8 register sets the i/o direction of pins for each bit. if "1" is set to the bit corresponding to a port, the port becomes an output port. if "0" is set to the bit corresponding to a port, the port becomes an input port table 4.10-3 "register functions of port 8" lists the register functions of port 8. table 4.10-3 register functions of port 8 register name data read write read/write address initial value port 8 data register (pdr8) 0 pin state is "l" "0" is set to the output latch. if port 8 operates as an output port, the "l" level is output to the pins. r/w 0027 h xxxxxxxx b 1 pin state is "h" "1" is set to the output latch. if port 8 operates as an output port, the "h" level is output to the pins. port 8 direction register (ddr8) 0 input port state output transistor operation is prohibited and a pin is made an input pin. r/w 0028 h 000x0000 b 1 output port state output transistor operation is allowed and a pin is made an output pin. r/w: read/write enabled x: undefined
138 chapter 4 i/o port n registers related to port 8 m a/d port input enable register (aden1) 002d h to use port 8 for analog input, set "1" to the corresponding bit of the aden1 register. this can help prevent the dc pass when an intermediate level is entered. m comparator input enable register (cier) 0059h to use port 8 for comparator input and to help prevent the dc pass when an intermediate level is entered, set "1" to the corresponding bit of the cier register. note: to use port 8 for port input, "0" must be set to the input enable bit of the aden1/cier registers.
139 4.10 port 8 4.10.2 operation of port 8 this section describes the operations of port 8. n operation of port 8 m operation as an output port ? if "1" is set to the corresponding ddr8 register bit, the port becomes an output port. ? the operation of the output transistor is allowed when port 8 operates as an output port and data of the output latch is output to the pins. ? if data is written into the pdr8 register, the data is retained on the output latch and then output directly to the pins. ? pin values can be read by reading the pdr8 register. m operation as an input port ? if "0" is set to the corresponding ddr8 register bit, the port becomes an input port. ? the output transistor is "off" and the pins are in high impedance when port 8 operates as an input port. ? if data is written into the pdr8 register, the data is retained on the output latch but is not output to the pins. ? pin values can be read by reading the pdr8 register. m operation during resource i/o ? set "0" to the ddr8 register corresponding to the resource input pin to use port 8 for resource input. m operation during a reset ? if cpu is reset, the value of the ddr8 register is initialized to "0". thus, the output transistor is turned "off" (input port) and the pins are put into high impedance. ? the pdr8 register is not initialized by a reset. thus, to use port 8 as an output port, output data must be set to the pdr8 register and the output must be set to the corresponding ddr8 register. ? the aden1/cier registers are initialized to "1" by a reset. thus, to use port 8 for port input, "0" must be set to the corresponding bits of the aden1/cier registers. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, the pins are put into high impedance because the output transistor is forced "off" regardless of the value of the ddr8 register. the input other than that of p84 is fixed to prevent leakage due to input opening.
140 chapter 4 i/o port table 4.10-4 "pin states of port 8" lists the pin states of port 8. table 4.10-4 pin states of port 8 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p80 to p87 general-purpose i/o port/ resource i/o hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
141 4.11 port 9 4.11 port 9 port 9 is a general-purpose i/o port which also serves for resource i/o. this section describes the functions of the general-purpose i/o port. the following shows the configuration of port 9, its pins, pin block diagrams, and the related register. n configuration of port 9 port 9 is made up of the following three elements: m port 9 ? general-purpose i/o pin/analog input pin (p90/an3, p91/da1, p92/da2) ? port 9 data register (pdr9) ? port 9 direction register (ddr9) n pins of port 9 port 9 has three cmos i/o pins. do not use these pins as a general-purpose port when resources are used. table 4.11-1 "pins of port 9" lists the pins of port 9. for the circuit type, see section 1.7 "pin description". table 4.11-1 pins of port 9 port name pin name function shared resource i/o type circuit type input output port 9 p90/an3 p90 general-purpose i/o analog input analog/ cmos cmos e p91/da1 p91 general-purpose i/o d/a converter output cmos cmos/ da m p92/da2 p92 general-purpose i/o d/a converter output
142 chapter 4 i/o port n block diagram of port 9 figure 4.11-1 block diagram of pins of port 9 (p90) p-ch n-ch ddr a/d input enable bit a/d converter channel select bit to a/d converter analog input pin pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register)
143 4.11 port 9 figure 4.11-2 block diagram of pins of port 9 (p91, p92) note: do not use the pins to be used as an analog input pin as a general-purpose port. n registers pdr9 and ddr9 of port 9 two registers pdr9 and ddr9 are available as the registers related to port 9. there is a 1:1 correspondence between the bits configuring each register and the pins of port 9. table 4.11-2 "correspondence between the registers and pins of port 9" lists the correspondence between the registers and pins of port 9. p-ch n-ch ddr from resource output from resource output enable bit pin pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register) table 4.11-2 correspondence between the registers and pins of port 9 port name bits of the related registers and corresponding pins port 9 pdr9, ddr9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 corresponding pinCCCCCp92p91p90
144 chapter 4 i/o port 4.11.1 registers of port 9 (pdr9, ddr9) this section describes the registers related to port 9. n functions of the registers of port 9 m port 9 data register (pdr9) the pdr9 register indicates the states of pins. thus, if the pins are set as output ports, the same values ("0" or "1") can be read as those of the output latch. however, if the pins are set as input ports, the values of the output latch cannot be read. since the values of the output latch rather than the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m port 9 direction register (ddr9) the ddr9 register sets the i/o direction of pins for each bit. if "1" is set to the bit corresponding to a port, the port becomes an output port. if "0" is set to the bit corresponding to a port, the port becomes an input port table 4.11-3 "register functions of port 9" lists the register functions of port 9. table 4.11-3 register functions of port 9 register name data read write read/write address initial value port 9 data register (pdr9) 0 pin state is "l" "0" is set to the output latch. if port 9 operates as an output port, the "l" level is output to the pins. r/w 0029 h xxxxxxxx b 1 pin state is "h" "1" is set to the output latch. if port 9 operates as an output port, the "h" level is output to the pins. port 9 direction register (ddr9) 0 input port state output transistor operation is prohibited and a pin is made an input pin. r/w 002a h xxxxx000 b 1 output port state output transistor operation is allowed and a pin is made an output pin. r/w: read/write enabled x: undefined
145 4.11 port 9 n register related to port 9 m a/d port input enable register (aden1) 002d h to use port 9 for analog input, set "1" to the corresponding bit of the aden1 register. this can also serve to prevent the dc pass when an intermediate level is entered. note: to use port 9 for port input, "0" must be set to the input enable bit of the aden1 registers.
146 chapter 4 i/o port 4.11.2 operation of port 9 this section describes the operations of port 9. n operation of port 9 m operation as an output port ? if "1" is set to the corresponding ddr9 register bit, the port becomes an output port. ? the operation of the output transistor is allowed when port 9 operates as an output port and data of the output latch is output to the pins. ? if data is written into the pdr9 register, the data is retained on the output latch and then output directly to the pins. ? pin values can be read by reading the pdr9 register. m operation as an input port ? if "0" is set to the corresponding ddr9 register bit, the port becomes an input port. ? the output transistor is "off" and the pins are in high impedance when port 9 operates as an input port. ? if data is written into the pdr9 register, the data is retained on the output latch but is not output to the pins. ? pin values can be read by reading the pdr9 register. m operation during resource i/o ? to use port 9 for analog input, set "1" to the corresponding bit of the ddr9 register and aden1 register corresponding to the analog input pin. ? since the d/a converter output takes precedence if the d/a converter output is allowed, settings of the corresponding ddr9 and pdr9 have no significance. m operation during a reset ? if cpu is reset, the value of the ddr9 register is initialized to "0". thus, the output transistor is turned "off" (input port) and the pins are put into high impedance. ? the pdr9 register is not initialized by a reset. thus, to use port 9 as an output port, output data must be set to the pdr9 register and the output must be set to the corresponding ddr9 register. ? the aden1 register is initialized to "1" by a reset. thus, to use port 9 for port input, "0" must be set to the corresponding bit of the aden1 register. m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, prohibition of the port input occurs regardless of the value of the ddr9 register and the pins are put into high impedance. the input is fixed to prevent leakage due to input opening.
147 4.11 port 9 table 4.11-4 "pin states of port 9" lists the pin states of port 9. table 4.11-4 pin states of port 9 pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset p90 general-purpose i/o port/analog input hi-z hi-z p91 to p92 general-purpose i/o port/d/a converter output hi-z hi-z spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance
148 chapter 4 i/o port 4.12 port a the port a is a general-purpose i/o port which also serves for lcd controller/driver segment output. the i/o port and lcd controller/driver segment output can be selected by the register setting this section describes the functions of the general- purpose i/o port. the following shows the configuration of the port a, its pins, a pin block diagram, and the related register. n configuration of port a the port a is made up of the following two elements: m port a ? general-purpose i/o pin/resource output (pa0/seg00 to pa7/seg07) ? port a data register (pdra) n pins of port a the port a has each eight n-ch open-drain i/o pins. do not use these pins as a general-purpose port when they are selected as a lcd controller/ driver segment output pin. table 4.12-1 "pins of port a" lists the pins of port a. for the circuit type, see section 1.7 "pin description". table 4.12-1 pins of port a port name pin name function shared resource i/o type circuit type input output port a pa0/seg00 pa0 general-purpose i/o seg00 lcdc segment output cmos n-ch open- drain j to to to pa7/seg07 pa7 general-purpose i/o seg07 lcd segment output
149 4.12 port a n block diagram of port a figure 4.12-1 block diagram of pins of port a note: do not set pdr=0 for the pins to be used as an lcd controller/driver segment. n register of port a one register pdra is available as the register related to port a. there is a 1:1 correspondence between the bits configuring the register pdra and the pins of port a. table 4.12-2 "correspondence between the register and pins of port a" lists the correspondence between the registers and pins of port a. n-ch from resource output enable bit from resource output pin pdr read pdr read (for bit manipulation instructions) pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus stop/watch mode spl: pin state designate bit of the standby control register (stbc) table 4.12-2 correspondence between the register and pins of port a port name bits of the related registers and corresponding pins port a pdra bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 corresponding pin pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0
150 chapter 4 i/o port 4.12.1 register of port a (pdra) this section describes the register related to port a. n functions of the register of port a m port a data register (pdra) the pdra register sets the states of pins. since the values of the output latch instead of the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m settings for lcd controller/driver segment output to use the port with the setting for lcd controller/driver segment output, set "1" to pdr of the pin to be used so that the lcd controller/driver segment output is not affected. table 4.12-3 "register functions of port a" lists the register functions of port a. n register related to port a m lcd controller/driver control register 3 (lcr3) 0016 h to use port a for lcd controller/driver output, set "0" to the corresponding bit of the lcr3 register. note: to use port a as a port, "1" must be set to the selection bit of the lcr3 register. table 4.12-3 register functions of port a register name data read write read/write address initial value port a data register (pdra) 0 pin state is "l" "0" is set to the output latch and the "l" level is output to the pins. r/w 0015 h 11111111 b 1 pin state is "h" "1" is set to the output latch and the "hi-z" level is output to the pins. r/w: read/write enabled hi-z: high impedance
151 4.12 port a 4.12.2 operation of the port a this section describes the operations of port a. n operation of port a m operation as an output port ? if data is written into the pdra register, the data is retained on the output latch and then output directly to the pins. ? when the port is used as an output port, it cannot be used for lcd controller/driver segment output. m operation for lcd controller/driver segment output ? set "1" to the bit of the pdra register corresponding to the lcd controller/driver segment output pin to put the output transistor into high impedance. m operation as an input port ? pin values can be read by reading the pdra register (when the lcd controller/driver segment output is not selected). m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, the pins are put into high impedance. the input is fixed to prevent leakage due to input opening. table 4.12-4 "pin states of port a" lists the pin states of port a. table 4.12-4 pin states of port a pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset pa0 to pa7 general-purpose i/o port/lcd controller/driver segment output/ uart output hi-z (*1) "l" output spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance *1: high impedance during lcd controller/driver segment output
152 chapter 4 i/o port 4.13 port b the port b is a general-purpose i/o port which also serves for lcd controller/driver i/ o. the i/o port and lcd controller/driver i/o can be selected by the register setting this section describes the functions of the general-purpose i/o port. the following shows the configuration of port a, its pins, pin block diagrams, and the related register. n configuration of port b port b is made up of the following two elements: m port b ? general-purpose i/o pin/resource i/o (pb0/v0 to pb3/v3, pb4/com0 to pb7/com03) ? port b data register (pdrb) n pins of the port b port b has each eight n-ch open-drain i/o pins. do not use these pins as a general-purpose port when they are selected as a lcd controller/ driver i/o pin. table 4.13-1 "pins of port b" lists the pins of port b. for the circuit type, see section 1.7 "pin description". table 4.13-1 pins of port b port name pin name function shared resource i/o type circuit type input output port b pb0/v0 pb0 general-purpose output v0 lcd controller/driver input - n-ch open- drain i to to to pb3/v3 pb3 general-purpose output v3 lcd controller/driver power input pb4/com0 pb4 general-purpose i/o com0 lcd controller/driver common output cmos n-ch open- drain j to to to pb7/com03 pb7 general-purpose i/o com0 lcd controller/driver common output
153 4.13 port b n block diagram of port b figure 4.13-1 block diagram of pins of port b (pb0 to pb3) figure 4.13-2 block fiagram of pins of port b (pb4 to pb7) note: do not set pdr=0 for the pins to be used as an lcd controller/driver segment. n register of port b one register pdrb is available as the register related to port b. there is a 1:1 correspondence between the bits configuring the register pdrb and the pins of port b. n-ch lcd controller/driver power supply pin pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus spl: pin state designate bit of the standby control register (stbc) n-ch from resource output enable bit from resource output pin pdr read pdr read (for bit manipulation instructions) pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus stop/watch mode spl: pin state designate bit of the standby control register (stbc)
154 chapter 4 i/o port table 4.13-2 "correspondence between the register and pins of port b" lists the correspondences between the registers and pins of port b. table 4.13-2 correspondence between the register and pins of port b port name bits of the related registers and corresponding pins port b pdrb bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 corresponding pin pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0
155 4.13 port b 4.13.1 register of port b (pdrb) this section describes the register related to port b. n functions of the register of port b m port b data register (pdrb) the pdrb register sets the states of pins. since the values of the output latch instead of the pins are read when a bit manipulation instruction (setb, clrb) is used, the values of the output latch whose bits are not manipulated do not change. m settings for lcd controller/driver i/o to use the port with the setting for lcd controller/driver i/o, set "1" to pdr of the pin to be used so that the lcd controller/driver i/o is not affected. table 4.13-3 "register functions of port b" lists the register functions of port b. n register related to port b m lcd controller/driver control register 4 (lcr4) 0018 h to use port b for lcd controller/driver i/o, set "0" to the corresponding bit of the lcr4 register. note: to use port b as a port, it is necessary to set "0" to the selection bit of the lcr4 register. table 4.13-3 register functions of port b register name data read write read/write address initial value port b data register (pdrb) 0 pin state is "l" "0" is set to the output latch and the "l" level is output to the pins. r/w (*1) 0017 h 11111111 b 1 pin state is "h" (*1) "1" is set to the output latch and the "hi-z" level is output to the pins. r/w: read/write enabled hi-z: high impedance *1: only pb4 to pb7 are read enabled. do not use instructions of the pwm set. "0" can always be read from pb0 to pb3.
156 chapter 4 i/o port 4.13.2 operation of port b this section describes the operations of port b. n operation of port b m operation as an output port ? if data is written into the pdrb register, the data is retained on the output latch and then output directly to the pins. ? when the port is used as an output port, it cannot be used for lcd controller/driver i/o. m operation for lcd controller/driver segment i/o ? set "1" to the bit of the pdrb register corresponding to the lcd controller/driver segment i/ o pin to put the output transistor into high impedance. m operation as an input port ? by reading the pdrb register, the values of only the pb4 to pb7 pins can be read (when the lcd controller/driver segment output is not selected). m operation in stop mode and watch mode ? if the pin state designate bit (stbc: spl) of the standby control register is set to "1" when a transition to the stop mode or watch mode occurs, the pins are put into high impedance. the input is fixed to prevent leakage due to input opening. table 4.13-4 "pin states of port b" lists the pin states of port b. table 4.13-4 pin states of port b pin name normal operation main sleep main stop (spl=0) sub-sleep sub-stop (spl=0) watch mode (spl=0) main stop (spl=1) sub-stop (spl=1) watch mode (spl=1) during reset pb0 to pb3 general-purpose i/o port/lcd controller/driver input hi-z (*1) lcd controller/ driver input pb4 to pb7 general-purpose i/o port/lcd controller/driver i/o hi-z (*1) "l" output spl: pin state designate bit of the standby control register (stbc: spl) hi-z: high impedance *1: high impedance cannot be specified during lcd controller/driver segment output
157 4.14 program example of the i/o ports 4.14 program example of the i/o ports this section shows a program example using the i/o port. n program example of the i/o ports m processing specifications ? turn on all led of seven segments (eight segment if dp is included) from the ports 0/1. ? the p00 pin corresponds to the anode common pin of led, and the pins p10 to p17 pins correspond to each segment pin. figure 4.14-1 "example of an 8-segment led connection" shows an example of an 8-segment led connection. figure 4.14-1 example of an 8-segment led connection m coding example pdr0 .equ 0000h ; address of the port 0 data register ddr0 .equ 0001h ; address of the port 0 direction register pdr1 .equ 0002h ; address of the port 1 data register ddr1 .equ 0003h ; address of the port 1 direction register ;----------main program--------------------------------------------- .section cseg, code, align = 1 ; [code segment] : clrb pdr0:0 ; set p00 to the "l" level. mov pdr1, #11111111b ; set the port 1 all to the "h" level mov ddr0, #11111111b ; set p00 for output, ; enabled by #xxxxxxx1b. mov ddr1, #11111111b ; set all bits of the port 1 for output : ends ;------------------------------------------------------------------- .end p00 p17 p16 p10 mb89570
158 chapter 4 i/o port
159 chapter 5 timebase timer this chapter describes the functions and operations of the timebase timer. 5.1 "overview of the timebase timer" 5.2 "configuration of the timebase timer" 5.3 "timebase timer control register (tbtc)" 5.4 "timebase timer interrupt" 5.5 "operation of the timebase timer" 5.6 "notes on using the timebase timer" 5.7 "program example of the timebase timer"
160 chapter 5 timebase timer 5.1 overview of the timebase timer the timebase timer is a 21-bit free-run counter that counts up in synchronization with the internal count clock (divide-by-two of the main clock oscillation) and provides the interval timer function in which four kinds of interval time can be selected. the timebase timer also supplies timer output for the oscillation stabilization wait time and an operating clock for the watchdog timer and others. the timebase timer stops its operations in a mode in which the main clock oscillation stops. n interval timer function the interval timer is a function used to generate an interrupt repeatedly at constant intervals. ? an interrupt occurs if the interval timer bit of the counter of the timebase timer overflows. ? the interval timer bit (interval time) can be selected from four kinds of interval time. table 5.1-1 "interval time of the timebase timer" lists the interval time of the timebase timer. table 5.1-1 interval time of the timebase timer internal count clock cycle interval time 2/f ch (0.2 m s) 2 13 /f ch (approx. 0.82 ms) 2 15 /f ch (approx. 3.3 ms) 2 18 /f ch (approx. 26.2 ms) 2 22 /f ch (approx. 419.4 ms) f ch : main clock oscillation values in ( ) shows the interval time when the main clock operates with 10 mhz oscillation.
161 5.1 overview of the timebase timer n clock supply function the clock supply function is a function used to supply timer output (four options) for the oscillation stabilization wait time of the main clock and the operating clock to part of the peripheral functions. table 5.1-2 "clocks supplied from the timebase timer" lists the cycles of clocks supplied to each peripheral function from the timebase timer. note: the oscillation cycle is unstable just after the oscillation start and the oscillation stabilization wait time serves as a guideline. table 5.1-2 clocks supplied from the timebase timer clock supply destination clock cycle remarks main clock oscillation stabilization wait time 2 14 /f ch (approx. 1.63 ms) selected by the oscillation stabilization wait time select bits (sycc: wt1, wt0) of the system clock control register in the clock controller 2 17 /f ch (approx. 113.1 ms) 2 18 /f ch (approx. 26.2 ms) watchdog timer 2 21 /f ch (approx. 209.7 ms) count-up clock of the watchdog timer lcd controller/driver 2 8 /f ch (approx. 25.6 m s) clock for frame cycle generation f ch : main clock oscillation values in ( ) shows the interval time when the main clock operates with 10 mhz oscillation
162 chapter 5 timebase timer 5.2 configuration of the timebase timer the timebase timer is made up of the following four blocks: ? timebase timer counter ? counter clear circuit ? interval timer selector ? timebase timer control register (tbtc) n block diagram of the timebase timer figure 5.2-1 block diagram of the timebase timer m timebase timer counter 21-bit up-counter using the count clock of divide-by-two of the main clock oscillation. this counter stops operating when the main clock oscillation stops. m counter clear circuit clears the counter when, in addition to the setting (tbr=0) by the tbtc register, a transition to the main stop mode (stbc: stp=1) or subclock mode (sycc: scs=0), or a power-on reset occurs. divide-by-two of f ch timebase timer counter to watchdog timer interval timer selector to oscillation stabilization wait time selector of clock controller counter clear circuit power-on reset stop mode start (in main clock mode) irq7 timebase timer interrupt of of of of tbc0 tbr tbc1 tbof tbie watchdog timer clear of: overflow f ch : main clock oscillation subclock mode start counter clear to lcd controller/driver timebase timer control register (tbtc) 2 1 2 2 2 3 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 20 2 21
163 5.2 configuration of the timebase timer m interval timer selector circuit to select one bit for the interval timer from four bits of the timebase timer counter. the overflow of the selected bit causes an interrupt. m timebase timer control register (tbtc) this register is used to select the interval time, clear the counter, control interrupts, and check the states.
164 chapter 5 timebase timer 5.3 timebase timer control register (tbtc) the timebase timer control register (tbtc) is used to select the interval time, clear the counter, control interrupts, and check the state. n timebase timer control register (tbtc) figure 5.3-1 timebase timer control register (tbtc) tbie 0 1 tbc1 0 0 1 1 tbc0 0 1 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 a h address 00xxx000 b initial value tbc0 tbr tbc1 r/w r/w w r/w r/w tbie interrupt request enable bit prohibit interrupt request output allow interrupt request output tbof overflow interrupt request flag bit no overflow of specified bit clear this bit no change and no effects on others 0 1 interval time select bits read write f ch : main clock oscillation tbof r/w : read/write enabled w : write only - : unused x : undefined :initial value overflow of specified bit tbr timebase timer initialization bit clear the counter of the timebase timer 0 1 read write "1" is always read no change and no effects on others 2 13 /f ch 2 15 /f ch 2 18 /f ch 2 22 /f ch
165 5.3 timebase timer control register (tbtc) table 5.3-1 explanation of functions of each bit of the timebase timer control register (tbtc) bit name function bit 7 tbof: overflow interrupt request flag bit ? this bit is set to "1" if the specified bit of the counter of the timebase timer overflows. ? if both this bit and the interrupt enable bit (tbie) are "1", an interrupt request is output. ? if "0" is written into this bit, the counter is cleared. if "1" is written, no change occurs and operations are not affected. bit 6 tbie: interrupt request enable bit ? bit to allow/prohibit interrupt request output to cpu. if both this bit and the overflow interrupt request flag bit (tbof) are "1", an interrupt request is output. bit 5 bit 4 bit 3 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 2 bit 1 tbc1, tbc0: interval time select bit ? bits to select the interval timer cycle ? bits for the interval timer of the counter of the timebase timer are specified. ? four kinds of interval time can be selected. bit 0 tbr: timebase timer initialization bit ? bit to clear the counter of the timebase timer ? if "0" is written into this bit, the counter is cleared to "000000 h ". if "1" is written, no change occurs and operations are not affected. reference: "1" is always read.
166 chapter 5 timebase timer 5.4 timebase timer interrupt as an interrupt source of the timebase timer, an overflow of the specified bit of the timebase timer counter is available (interval timer function). n interrupt when the interval timer function is active if an overflow of the selected interval timer bit occurs after the counter is counted up by the internal count clock, the overflow interrupt request flag bit (tbtc: tbof) is set to "1". at this time, if the interrupt request enable bit is set (tbtc: tbie=1), an interrupt request to cpu (irq7) is generated. clear the interrupt request by writing "0" into the tbof bit using an interrupt processing routine. the tbof bit is set whenever an overflow of the specified bit occurs regardless of the value of the tbie bit. note: to allow interrupt request output (tbie=1) after releasing a reset, clear (tbof=0) the tbof bit at the same time. reference: if the tbie bit is changed from prohibition to permission (0 --> 1) when the tbof bit is "1", an interrupt request is issued immediately. if the counter clear (tbtc: tbr=0) and an overflow of the selected bit occur at the same time, the tbof bit is not set. n oscillation stabilization wait time and timebase timer interrupts if interval time shorter than the oscillation stabilization wait time of the main clock is set, an interval interrupt request (tbtc: tbof=1) of the timebase timer is generated when the operation in main clock mode starts. in this case, prohibit (tbtc: tbie=0) interrupts of the timebase timer when making a transition to a mode in which the oscillation of the main clock stops (main stop and subclock modes). n register and vector table related to the timebase timer interrupts for the interrupt operations, see section 3.4.2 "interrupt processing". table 5.4-1 register and vector table related to the timebase timer interrupts interrupt name interrupt level setting register vector table address register bit to be set upper lower irq7 ilr2 (007c h ) l71 (bit 7) l70 (bit 6) ffec h ffed h
167 5.5 operation of the timebase timer 5.5 operation of the timebase timer the timebase timer provides the interval timer function and supplies the clock to part of the peripheral functions. n operation of the interval timer function (timebase timer) the setting in figure 5.5-1 "setting of the interval timer function" is required for the operation of the interval timer function. figure 5.5-1 setting of the interval timer function the counter of the timebase timer continues to count up provided the main clock oscillates in synchronization with the internal count clock (divide-by-two of the main clock oscillation). if the counter is cleared (tbr=0), it starts counting up from "0". if an overflow of the bit for the interval timer occurs, "1" is set to the overflow interrupt request flag bit (tbof). that is, starting when clearing occurs, an interrupt request is generated at regular intervals of the selected time. n operation of the clock supply function the timebase timer is also used as a timer to generate the oscillation stabilization wait time of the main clock. counting of the oscillation stabilization wait time starts when the counter of the timebase timer is cleared and ends when an overflow of the bit for oscillation stabilization wait time occurs. three kinds of oscillation stabilization wait time can be selected by the setting of the oscillation stabilization wait time select bits (sycc: wy1, wt0) of the system clock control register. the timebase timer supplies the clock to the watchdog timer, a/d converter, and lcd controller/ driver. when the counter of the timebase timer is cleared, operations of the continuous activation cycles of the a/d converter and those of the frame cycles of the lcd controller/driver are affected. the counter of the watchdog timer is cleared at the same time provided the timebase timer output is selected (wdtc: cs=0). n operations of the time-based timer figure 5.5-2 "operations of the timebase timer" shows the operations in the following states: ? when a power-on reset occurs ? when a transition to the sleep mode occurs during operation of the interval timer function in main clock mode ? when a transition to the main stop mode occurs ? when the counter clear is requested in subclock mode and main stop mode, the timebase timer is cleared and its operation is stopped. when returning from the subclock mode or main stop mode, the oscillation stabilization wait time is counted by the timebase timer. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tbtc tbc0 tbr tbc1 10 0 tbie tbof : bit used 1 : 1 is set 0 : 0 is set
168 chapter 5 timebase timer figure 5.5-2 operations of the timebase timer tbof bit 1fffff h 00000 h counter value oscillation stabilization wait overflow cpu operation start power-on reset (option) interval cycle (tbtc: tbc1, tbco=11 b ) clear by an interrupt processing routine sleep stop slp bit (stbc register) stp bit (stbc register) counter clear (tbtc: tbr=0) clearing by transition to the main stop mode : indicates the oscillation stabilization wait time sleep release by irq7 tbie bit stop release by an external interrupt when "11 b " is set to the interval time select bits (tbtc: tbc1, tbc0) of the timebase timer control register (2 22 /f ch ).
169 5.6 notes on using the timebase timer 5.6 notes on using the timebase timer the following describes the precautions to take when using the timebase timer. n notes on using the timebase timer m precautions when setting the timebase timer with programs because it is impossible to return from interrupt processing if the interrupt request flag bit (tbtc: tbof) is "1" and the interrupt request enable bit (tbtc: tbie=1) is allowed, the tbof bit must be cleared. m clearing the timebase timer the timebase timer is cleared, in addition to clearing by the timebase timer initialization bit (tbtc: tbr=0), when the oscillation stabilization wait time of the main clock is required. if the timebase timer is selected (wdtc: cs=0) as the count clock of the watchdog timer, the watchdog timer is cleared when the timebase timer is cleared. m using the timebase timer as a timer for the oscillation stabilization wait time since the main clock oscillation is stopped when the power is turned on or is in main stop mode or subclock mode, the oscillator takes the oscillation stabilization wait time of the main clock. the appropriate oscillation stabilization wait time must be selected according to the type of resonator connected to the oscillator (clock generator) of the main clock. for details, see section 3.7.5 "oscillation stabilization wait time" m precautions for peripheral functions to which the clock is supplied from the timebase timer in a mode in which the main clock oscillation stops, the counter is cleared and the timebase timer stops its operation. if the counter of the timebase timer is cleared, the "h" level of the clock supplied by the timebase timer is short and its "h" level may be longer by a 1/2 cycle at the most because the output originates from the initial state. though the clock for the watchdog timer is also output from the initial state, the watchdog timer works in normal cycles because the counter of the watchdog timer is cleared simultaneously. figure 5.6-1 "effects on the lcd controller/driver when the timebase timer is cleared" shows the effects on the lcd controller/driver when the timebase timer is cleared.
170 chapter 5 timebase timer figure 5.6-1 effects on the lcd controller/driver when the timebase timer is cleared counter value xxx3ff h xxx200 h xxx000 h counter clearing by program (tbtc: tbr=0) supply clock to lcd controller/driver x: arbitrary value, cleared to "0"
171 5.7 program example of the timebase timer 5.7 program example of the timebase timer the following shows a program example of the timebase timer. n program example of the timebase timer m processing specifications generate the interval timer interrupt of 2 18 /f ch (f ch : main clock oscillation) repeatedly. the interval time at this time is about 26 ms (for 10 mhz operations).
172 chapter 5 timebase timer m coding example tbtc .equ 0000ah ; address of the timebase timer control register tbof .equ tbtc:7 ; definition of interrupt request flag bit ilr2 .equ 007ch ; address of the interrupt level setting register 2 .section int_v, data, locate=0 ; [data segment] .org 0ffech irq7 .data.h wari ; setting interrupt vector ;int_v ends ;----main program----------------------------------------------------- .section cseg, code, align=1 ; [code segment] ; stack pointer (sp) and other are assumed to have been initialized : clri ; interrupt disable mov ilr2,#01111111b ; setting interrupt level(level 1) mov tbtc,#01000100b ; clearing interrupt request flag, enabling interrupt request output, selecting 2 18 /f ch , and clearing timebase timer seti ; interrupt enable : ;----interrupt program------------------------------------------------ wari clrb tbof ; clearing interrupt request flag pushw a xchw a,t pushw a : user processing : popw a xchw a, t popw a reti ends ; -------------------------------------------------------------------- .end
173 chapter 6 watchdog timer this chapter describes the functions and operations of the watchdog timer. 6.1 "overview of the watchdog timer" 6.2 "configuration of the watchdog timer" 6.3 "watchdog timer control register (wdtc)" 6.4 "operation of the watchdog timer" 6.5 "notes on using the watchdog timer" 6.6 "program example of the watchdog timer"
174 chapter 6 watchdog timer 6.1 overview of the watchdog timer the watchdog timer is a 1-bit timer which accepts the output of either the timebase timer operating with the main clock or the watch prescaler operating with the subclock as the count clock. if the watchdog timer is not cleared for a specified period of time after activation, cpu is reset. n watchdog timer function the watchdog timer is a counter against program runaway. once the watchdog timer is activated, it is necessary to continue clearing it periodically within a specified period of time. if the watchdog timer is not cleared for a specified period of time, for example, because the program slips into an endless loop, a watchdog reset of the four instruction cycles is generated to cpu. as the count clock of the watchdog timer, the output of either the timebase timer or watch prescaler can be selected. the interval time of the watchdog timer is as listed in table 6.1-1 "interval time of the watchdog timer". if the watchdog timer is not cleared, a watchdog reset occurs between the minimum and maximum times. clear the counter within the minimum time of this table. for the minimum and maximum times of the interval time of the watchdog timer, see section 6.4 "operation of the watchdog timer" note: the counter of the watchdog timer is cleared at the same time the timebase timer is cleared (tbtc: tbr=0) in a state in which the output of the timebase timer is selected as the count clock, or it is cleared at the same time the watch prescaler is cleared (wpcr: wclr=0) in a state in which the output of the watch prescaler is selected as the count clock. thus, if the counter (timebase timer or watch prescaler) used as the count clock is cleared repeatedly within an interval time of the watchdog timer, the watchdog timer will not function. reference: if a transition to the sleep mode, stop mode, or watch mode occurs, the counter of the watchdog timer is cleared and will not operate until normal operation (run state) is resumed. table 6.1-1 interval time of the watchdog timer count clock timebase timer output (for main clock oscillation 10 mhz) watch prescaler output (for subclock oscillation 32. 768 khz) minimum time approx. 209.7 ms (*1) 500 ms (*2) maximum time approx. 419.4 ms 1000 ms *1: divide-by-two of the main clock oscillation (f ch ) x count of the timebase timer (2 20 ) *2: cycle of the subclock oscillation (f cl ) x count of the watch prescaler (2 14 )
175 6.2 configuration of the watchdog timer 6.2 configuration of the watchdog timer the watchdog timer is made up of the following six blocks: ? count clock selector ? watchdog timer counter ? reset control circuit ? watchdog timer clear selector ? counter clear control circuit ? watchdog timer control register (wdtc) n block diagram of the watchdog timer figure 6.2-1 block diagram of the watchdog timer m count clock selector the count clock selector selects the count clock of the watchdog timer counter. as the count clock, the output of either the timebase timer or the watch prescaler can be selected. m watchdog timer counter (1-bit counter) the watchdog timer counter is a 1-bit counter whose count clock is the output of either the timebase timer or the watch prescaler. reset control circuit 1-bit counter overflow rstx watchdog timer control register (wdte) watchdog timer count clock selector 2 21 /f ch (timebase timer output) 2 14 /f cl (watch prescaler output) counter clear control circuit sleep mode start stop mode start watch mode start watchdog timer clear selector clear signal from timebase timer clear signal from watch prescaler wte0 cs wte3 wte2 wte1 clear start f ch : main clock oscillation f cl : sub-clock oscillation
176 chapter 6 watchdog timer m reset control circuit the reset control circuit generates a reset signal to cpu when an overflow of the watchdog timer counter occurs. m watchdog timer clear selector the watchdog timer clear selector selects the watchdog timer clear signal from the timebase timer or watch prescaler simultaneously with the count clock selector. m counter clear control circuit the counter clear control circuit controls the watchdog timer counter clearing and operation stop. m watchdog timer control register (wdtc) the watchdog timer control register is used to select the count clock and activate/clear the watchdog timer counter. since this register is write only, bit manipulation instructions cannot be used.
177 6.3 watchdog timer control register (wdtc) 6.3 watchdog timer control register (wdtc) the watchdog timer control register (wdtc) is used to activate/clear the watchdog timer. n watchdog timer control register (wdtc) figure 6.3-1 watchdog timer control register (wdtc) wte3 0 otherwise bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 9 h address wte0 watchdog control bit - activate watchdog timer (for the 1st write after reset) - clear watchdog timer (for the 2nd and later write after reset) cs wte3 wte2 wte1 wwww wte2 1 wte1 0 wte0 1 0xxxxxxx b initial value r/w : read/write enabled w : write only - : unused x : undefined : initial value (note) since this register is write only, bit manipulation instructions cannot be used. *1: f ch : main clock oscillation *2: f cl : sub-clock oscillation cs 0 1 count clock switch bit timebase timer output cycle (2 21 /f ch *1 ) watch prescaler output cycle (2 14 /f cl *2 ) r/w no operation
178 chapter 6 watchdog timer table 6.3-1 explanation of the functions of each bit of the watchdog timer control register (wdtc) bit name function bit 7 cs: count clock switch bit ? select the count clock of the watchdog timer when activating the watchdog timer. ? as the count clock, the output of either the timebase timer or the watch prescaler can be selected. note: ? to use the subclock mode, select the output of the watch prescaler. ? select the count clock simultaneously with activation of the watchdog timer and do not change it after the activation. ? bit manipulation instructions cannot be used. bit 6 bit 5 bit 4 unused bist ? the read value is undefined. ? writing has no effect on operation. bit 3 bit 2 bit 1 bit 0 wte3, wte2, wte1, wte0: watchdog control bit ? if "0101 b " is written into these bits, the watchdog timer is activated (the 1st write after reset) or cleared (the 2nd or later write after reset). ? writing anything other than "0101 b " does not affect operations. note: "1111 b " is read. bit manipulation instructions cannot be used.
179 6.4 operation of the watchdog timer 6.4 operation of the watchdog timer the watchdog timer generates a watchdog reset when the watchdog timer counter overflows. n operation of the watchdog timer m activating the watchdog timer ? the watchdog timer can be activated by writing the 1st "0101 b " into the watchdog control bits (wdtc: wte3 to 0) of the watchdog timer control register after a reset. at this time, specify the count clock switch bit (wdtc: cs) simultaneously. ? a watchdog timer that is activated can only be stopped by a reset. m clearing the watchdog timer ? the counter of the watchdog timer can be cleared by writing the 2nd or subsequent "0101 b " into the watchdog control bits (wdtc: wte3 to 0) of the watchdog timer control register after a reset. ? if the counter is not cleared within the interval time of the watchdog timer, an overflow of the counter occurs and an internal reset signal of the four instruction cycles is generated. m watchdog timer interval time the interval time is changed by the timing of clearing the watchdog timer. figure 6.4-1 "watchdog timer clearing and interval time" shows the relations between the clearing timing of the watchdog timer and the interval time when the output of the timebase timer is selected as the count clock (if the main clock oscillation is 10 mhz).
180 chapter 6 watchdog timer figure 6.4-1 watchdog timer clearing and interval time timebase timer count clock output maximum time watchdog reset watchdog clear watchdog 1 bit counter timebase timer count clock output minimum time watchdog reset watchdog 1 bit counter 209.7ms 419.4ms overflow overflow watchdog clear
181 6.5 notes on using the watchdog timer 6.5 notes on using the watchdog timer the following describes the precautions to take when using the watchdog timer. n notes on using the watchdog timer m stopping the watchdog timer a watchdog timer that is activated can only be stopped by a reset. m selecting the count clock the count clock switch bit (wdtc: cs) can be rewritten only if "0101 b " is written into the watchdog control bits (wdtc: wte3 to 0) when the watchdog timer is activated. thus, a write operation by bit manipulation instructions is not possible. do not change the settings after activation. since the main clock oscillation stops in subclock mode, the timebase timer does not operate. to enable operation of the watchdog timer in subclock mode, the watch prescaler (wdtc: cs=1) must be selected as the count clock in advance. m clearing the watchdog timer ? if the counter (timebase timer or watch prescaler) used as the count clock of the watchdog timer is cleared, the counter of the watchdog timer is cleared at the same time. ? if a transition to the sleep mode, stop mode, or watch mode occurs, the counter of the watchdog timer is cleared. m precautions when creating a program when creating a program in which the watchdog timer is cleared repeatedly in the main loop, the processing time of the main loop including interrupt processing must be equal to or less than the minimum watchdog timer interval time. m operations in subclock mode if a watchdog reset occurs in subclock mode, operation starts in main clock mode after taking the oscillation stabilization wait time. at this time, a reset signal is output during oscillation stabilization wait time.
182 chapter 6 watchdog timer 6.6 program example of the watchdog timer the following shows a program example in which the watchdog timer is used. n program example of the watchdog timer m processing specifications ? select the watch prescaler just after starting the program to activate the watchdog timer. ? clear the watchdog timer each time in a loop of the main program. ? the main loop must make a round in less than the interval minimum time (about 335.5 ms for 12.5 khz operation), including the interrupt processing time, of the watchdog timer.
183 6.6 program example of the watchdog timer m coding example wdtc .equ 0009h ; address of the watchdog timer control register wdt_clr .equ 10000101b .section vect, data, locate=0 ; [data segment] .org 0fffeh rst_v .data.h prog ; setting reset vector ;vect ends ;----main program--------------------------------------------------- .section cseg, code, align=1 ; [code segment] prog ; initialization routine for reset movw sp,#0280h ; setting initial value of stack pointer (for interrupt) : initializing interrupt or other peripheral functions : init mov wdtc,#wdt_clr ; activating watchdog timer selection of the watchdog prescaler as the count clock : main mov wdtc,#wdt_clr ; clearing watchdog timer : user processing (interrupt may occur in this processing.) : jmp main ; ensure that the time necessary for running the loop is shorter than the minimum time interval of the watchdog timer. ends ;------------------------------------------------------------------- .end
184 chapter 6 watchdog timer
185 chapter 7 watch prescaler this chapter describes the functions and operations of the watch prescaler. 7.1 "overview of the watch prescaler" 7.2 "configuration of the watch prescaler" 7.3 "watch prescaler control register (wpcr)" 7.4 "watch prescaler interrupt" 7.5 "operation of the watch prescaler" 7.6 "notes on using the watch prescaler" 7.7 "program example of the watch prescaler"
186 chapter 7 watch prescaler 7.1 overview of the watch prescaler the watch prescaler is a 17-bit free-run counter that counts up in synchronization with the subclock generated in the clock generator and has an interval timer function that provides for the selection of six kinds of interval time. the watch prescaler also supplies the timer output of subclock oscillation stabilization wait time and the operating clock of the watchdog and other timers. n interval timer function (watch interrupt) the interval timer function is a function used to generate an interrupt repeatedly at regular intervals using the subclock as the count clock. ? an interrupt is generated by divide-by output for the interval timer of the watch prescaler. ? four kinds of divide-by output (interval time) for the interval timer can be selected. ? the counter of the watch prescaler can be cleared. table 7.1-1 "interval time of the watch prescaler" lists the interval time of the watch prescaler. note: if a resonator is not connected to the subclock, the watch prescaler cannot be used. n clock supply function the clock supply function of the watch prescaler is a function used to supply the timer output (one) for oscillation stabilization wait time of the subclock and the clock for the watchdog timer. table 7.1-2 "clocks supplied from the watch prescaler" lists the clock cycles supplied to each table 7.1-1 interval time of the watch prescaler subclock cycle interval time 1/f cl (approx. 30.5 m s) 2 10 /f cl (31.25 ms) 2 13 /f cl (0.25 s) 2 14 /f cl (0.50 s) 2 15 /f cl (1.00 s) 2 16 /f cl (2.00 s) 2 17 /f cl (4.00 s) f cl : subclock oscillation values in ( ) represent the interval time when the subclock oscillation is operating at 32.768 khz.
187 7.1 overview of the watch prescaler peripheral function from the watch prescaler. reference: because the oscillation cycles are unstable just after the oscillation starts, the oscillation stabilization wait timer serves as a guideline. table 7.1-2 clocks supplied from the watch prescaler subclock supply destination subclock cycle remarks subclock oscillation stabilization wait time 2 15 /f cl (1.00 s) do not make a transition to the subclock mode during oscillation stabilization wait time watchdog timer 2 14 /f cl (0.5 s) count-up clock of the watchdog timer f cl : subclock oscillation values in ( ) represent the subclock cycles when the subclock oscillation is operating at 32.768 khz.
188 chapter 7 watch prescaler 7.2 configuration of the watch prescaler the watch prescaler comprises the following blocks: ? watch prescaler counter ? counter clear circuit ? interval timer selector ? watch prescaler control register (wpcr) n block diagram of the watch prescaler figure 7.2-1 block diagram of the watch prescaler m watch prescaler counter 17-bit up-counter using the subclock oscillation as the count clock. m counter clear circuit the counter clear circuit clears the counter when, in addition to the setting by the wpcr register (wclr=0), a transition to the sub-stop mode (stbc: stp=1) or a power-on reset occurs. m interval timer selector circuit to select one divide-by output from six kinds of divide-by output from the watch prescaler counter. the falling edges of the selected divide-by output become an interrupt source. f cl : subclock oscillation values in ( ) represent the cycles when the subclock oscillation is operating at 32.768 khz. wclr wie wif ws1 ws0 counter clear circuit interval timer selector 1 0 3 25 4 7 68 10 912 11 14 13 power-on reset stop mode start (in subclock mode) f cl watchdog timer clear to oscillation stabilization wait timer selector in clock controller irq8 clock interrupt watch prescaler counter to watchdog timer watch prescaler control register (wpcr) 15 16 ws2 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17
189 7.2 configuration of the watch prescaler m watch prescaler control register (wpcr) this register is used to select the interval time, clear the counter, control interrupts, and check status.
190 chapter 7 watch prescaler 7.3 watch prescaler control register (wpcr) the watch prescaler control register (wpcr) is a register used to select the interval time, clear the counter, control interrupts, and check status. n watch prescaler control register (wpcr) figure 7.3-1 watch prescaler control register (wpcr) wie 0 1 ws1 0 0 1 1 0 0 ws0 0 1 0 1 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 b h address 00xx0000 b initial value ws0 wclr ws1 r/w r/w r/w r/w r/w wie interrupt request enable bit prohibit interrupt request output allow interrupt request output wif watch interrupt request flag bit no interval interrupt interval interrupt present clear this bit no change and does not affect others 0 1 watch interrupt interval time select bit read f cl : subclock oscillation wif r/w: read/write enabled - : unused x : undefined : initial value wclr watch prescaler clear bit 0 1 clear the watch prescaler no change and does not affect others "1" is always read read write write ws2 r/w ws2 0 0 0 0 1 1 2 10 /f cl 2 13 /f cl 2 14 /f cl 2 15 /f cl 2 16 /f cl 2 17 /f cl
191 7.3 watch prescaler control register (wpcr) table 7.3-1 explanation of the functions of each bit of the watch prescaler control register (wpcr) bit name function bit 7 wif: watch interrupt request flag bit ? "1" is set by the falling edges of the selected divide-by output for interval timer. ? if both this bit and the interrupt request enable bit (wie) are "1", an interrupt request is output. ? this bit is cleared if "0" is written into this bit. if "1" is written, no change occurs and no operation is affected. bit 6 wie: interrupt request enable bit ? bit to allow/prohibit interrupt request output to cpu. ? if both this bit and the watch interrupt request flag bit (wie) are "1", an interrupt request is output. bit 5 bit 4 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 3 bit 2 bit 1 ws2, ws1, ws0: watch interrupt interval time select bit ? bits to select the interval timer cycle ? bits for the interval timer of the counter of the watch prescaler are specified. ? six kinds of interval time can be selected. bit 0 wclr: watch prescaler clear bit ? bit to clear the counter of the watch prescaler ? if "0" is written into this bit, the counter is cleared to "000000 h ". if "1" is written, no change occurs and no operation is affected. reference: "1" is always read.
192 chapter 7 watch prescaler 7.4 watch prescaler interrupt the watch prescaler generates interrupt requests using the falling edges of the selected divide-by output (interval timer function). n interrupt when the interval timer function is active (watch interrupt) the counter for the watch prescaler counts up using the subclock oscillation. when the specified interval time passes, if not in main stop mode, the watch interrupt request flag bit (wpcr: wif=1) is set to "1". at this time, if the interrupt request enable bit is set (wpcr: wie=1), an interrupt request to cpu (irq8) is issued. clear the interrupt request to "0" by writing "0" into the wif bit using an interrupt processing routine. the wif bit is set whenever the specified divide-by output falls regardless of the value of the wie bit. note: to allow interrupt request output (wie=1) after releasing a reset, clear (wif=0) the wif bit at the same time. if the wie bit is changed from prohibition to permission (0 --> 1) when the wif bit is "1", an interrupt request is issued immediately. if the counter clear (wpcr: wclr=0) and an overflow of the selected bit occur at the same time, the wif bit is not set. n oscillation stabilization wait time and watch interrupts if an interval time period shorter than the oscillation stabilization wait time of the subclock is set, a watch interrupt request (wpcr: wif=1) of the watch prescaler is issued when returning from the sub-stop mode following an external interrupt. in this case, prohibit (wpcr: wie=0) interrupts of the watch prescaler when making a transition to the sub-stop mode. n register and vector table related to the watch prescaler interrupts table 7.4-1 "register and vector table related to the watch prescaler interrupts" lists the register and vector table related to the watch prescaler interrupts. for interrupt operations, see section 3.4.2 "interrupt processing". table 7.4-1 register and vector table related to the watch prescaler interrupts interrupt name interrupt level setting register vector table address register bit to be set upper lower irq8 ilr3 (007d h ) l81 (bit 1) l80 (bit 0) ffea h ffeb h
193 7.5 operation of the watch prescaler 7.5 operation of the watch prescaler the watch prescaler operates to provide the interval timer function and clock supply function. n operation of the interval timer function (watch prescaler) the setting in figure 7.5-1 "setting of the interval timer function" is required for the operation of the interval timer function. figure 7.5-1 setting of the interval timer function the 15-bit counter of the watch prescaler continues to count up the subclock provided the subclock oscillates. if the counter is cleared (wclr=0), it starts to count up from "00000 h ". when "1ffff h " is reached, counting continues starting from "00000 h ". when a falling edge is generated in the selected divide-by output for the interval timer, if not in main stop mode, "1" is set to the watch interrupt request flag bit (wif). that is, starting with the time when cleared, a watch interrupt request is generated at regular intervals of the selected time. n operation of the clock supply function the watch prescaler is also used as a timer to generate the oscillation stabilization wait time of the subclock. counting of the oscillation stabilization wait time of the subclock (2 15 /f cl , f cl : subclock oscillation) starts when the watch prescaler is cleared and ends when the highest bit falls. the watch prescaler supplies the clock to the watchdog timer and buzzer output. when the counter of the watch prescaler is cleared, operations of the buzzer output are affected. the counter of the watchdog timer is cleared at the same time if the watch prescaler output is selected (wdtc: cs=1). n operations of the watch prescaler figure 7.5-2 "operations of the watch prescaler" shows the counter values if a transition to the sleep mode or stop mode occurs, or the counter clearing is requested when the interval timer function is operating in subclock mode. the transition to the watch mode is the same as that to the sub-sleep mode. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpcr ws0 wclr ws1 10 0 wie wif : bit used 1 : 1 is set 0 : 0 is set ws2
194 chapter 7 watch prescaler figure 7.5-2 operations of the watch prescaler wif bit 1ffff h 00000 h counter value power-on reset interval cycle clearing by an interrupt processing routine slp bit (stbc register) stp bit (stbc register) counter clear (wpcr: wclr=0) clearing by transition to the sub-stop mode sleep release by irq8 wie bit stop release by an external interrupt subclock oscillation stabilization wait time subclock oscillation stabilization wait time sub-sleep sub-stop if "101 b " is set to the interrupt interval time select bits (wpcr: ws2, ws1, ws0) of the watch prescaler control register (2 17 /f cl )
195 7.6 notes on using the watch prescaler 7.6 notes on using the watch prescaler the following describes the precautions when using the watch prescaler. the watch prescaler cannot be used when a single clock source is specified with the option setting. n notes on using the watch prescaler m precautions when setting the watch prescaler in programs it is impossible to return from interrupt processing if the interrupt request flag bit (wpcr: wif) is "1" and the interrupt request enable bit is set (wpcr: wif=1). the wif bit must be cleared. m clearing the watch prescaler the watch prescaler is cleared, in addition to clearing by the watch prescaler clear bit (wpcr: wclr=0), when the oscillation stabilization wait time of the subclock is required. if the watch prescaler is selected (wdtc: cs=1) as the count clock of the watchdog timer, the watchdog timer is also cleared when the watch prescaler is cleared. m using the watch prescaler as a timer for the oscillation stabilization wait time since the subclock oscillation is stopped when the power is turned on or operating in sub-stop mode, the oscillator takes the oscillation stabilization wait time using the watch prescaler after activating operations. do not make a transition from the main clock mode to the subclock mode during oscillation stabilization wait time, such as just after power-on. the oscillation stabilization wait time of the subclock is fixed. for details, see section 3.7.5 "oscillation stabilization wait time". m precautions when using watch interrupts in main stop mode, the watch prescaler performs a count operation but a watch interrupt (irq8) does not occur. m precautions when using the peripheral functions that use clocks supplied from the prescaler. if the counter of the watch prescaler is cleared, the "h" level of the clock supplied by the watch prescaler is short and its "l" level may be longer by a maximum of 1/2 cycle because the output originates from the initial state. though the clock for the watchdog timer is also output from the initial state, the watchdog timer works in normal cycles because the counter of the watchdog timer is cleared simultaneously.
196 chapter 7 watch prescaler 7.7 program example of the watch prescaler the following shows a program example of the watch prescaler. n program example of the watch prescaler m processing specifications generate the watch interrupt of 2 15 /f cl (f cl : subclock oscillation) repeatedly. the interval time is about 1 s (for 32.768 khz operation).
197 7.7 program example of the watch prescaler m coding example wpcr .equ 000bh ; address of the watch prescaler control register wif .equ wpcr:7 ; definition of watch interrupt request flag bit ilr3 .equ 007dh ; address of the interrupt level setting register .section int_v, data, locate=0 ; [data segment] .org 0ffeah irq8 .data.h wari ; setting interrupt vector ;int_v ends ;----main program--------------------------------------------------- ----- .section cseg, code, align=1 ; [code segment] ; stack pointer (sp) and other are assumed to have been initialized : clri ; interrupt disable mov ilr3,#11111110b ; setting interrupt level (level 2) mov wpcr,#01000110b ; clearing interrupt request flag, enabling interrupt request output, selecting 2 15 /f cl , and clearing watch prescaler seti ; interrupt enable : ;----interrupt program------------------------------------------------ wari clrb wif ; clearing interrupt request flag pushw a xchw a,t pushw a : user processing : popw a xchw a, t popw a reti ends ;------------------------------------------------------------------- .end
198 chapter 7 watch prescaler
199 chapter 8 8/16-bit timer/counter this chapter describes the functions and operations of the 8/16-bit timer/counter. 8.1 "overview of the 8/16-bit timer/counter" 8.2 "configuration of the 8/16-bit timer/counter" 8.3 "pins of the 8/16-bit timer/counter" 8.4 "registers of the 8/16-bit timer/counter" 8.5 "8/16-bit timer/counter interrupts" 8.6 "operation of the interval timer function" 8.7 "operation of the counter function" 8.8 "operation of the square wave output initial setting function" 8.9 "operation of stopping and restarting the 8/16-bit timer/counter" 8.10 "status of the 8/16-bit timer/counter in each mode" 8.11 "notes on using the 8/16-bit timer/counter"
200 chapter 8 8/16-bit timer/counter 8.1 overview of the 8/16-bit timer/counter for timer 1, either the interval timer function or the counter function can be selected. the former function counts up in synchronization with one of the three types of internal count clocks. the latter function counts up according to a clock that is input to the external pin. this output can be used to output square waves of a pre-specified frequency. for timer 2, only the interval timer function that counts up in synchronization with one of the three types of internal count clock can be selected. this output can be used to output square waves of a pre-specified frequency. timer 2 is linked to timer 1 in the 16-bit mode. n interval timer function the interval timer function repeatedly generates an interrupt in pre-specified intervals. additionally, it can output square waves of a pre-specified frequency by reversing the output level of the pins at every interval. ? in the 8-bit mode, timers 1 and 2 operate as two independent timers. each of the timers can perform the interval timer operation from the count clock cycle to that times 2 8 . ? in the 16-bit mode, timers 1 and 2 operate as one 16-bit timer with the former as the lower and the latter as the upper. the timer can perform the interval timer operation from the count clock cycle to that times 2 16 . ? the count clock can be selected from one of the three types of internal count clocks (selecting the external clock for timer 1 selects the operation as the counter function.) ? the output cycle of timer 1 of the 8/16-bit timer/counter can be used as the consecutive start clock for the a/d converter. table 8.1-1 "channels of the 8/16-bit timer/counter and the pins that output square waves" shows the channels of the 8/16-bit timer/counter and the pins that output square waves using this timer output. table 8.1-2 "timer 1 interval time and square wave output range in the 8-bit mode" to table 8.1-4 "interval time and square wave output range in the 16-bit mode" shows the interval time and square wave output range in each of the operation modes. table 8.1-1 channels of the 8/16-bit timer/counter and the pins that output square waves channel 8/16-bit timer/counter 8-bit timer timer 1 timer 2 output pin 8-bit mode t01 t02 16-bit mode t01
201 8.1 overview of the 8/16-bit timer/counter m example of calculating the interval time and the square wave frequency assuming the original oscillation of the main clock (f ch ) as 10 mhz and the timer 1 data register (t1dr) value as "ddh (221)", calculate as follows the timer 1 interval time as well as the frequency of square waves that are output from the t01 pin when timer 1 continuously operates without changing this t1dr register value: note that the system clock control register (sycc) is used to select the fastest clock (cs1, cs0 = 11 b , 1 instruction cycle = 4/f ch ) in the main clock mode (scs=1). interval time = (2 x 4/f ch x (t1dr register value + 1) = (8/10 mhz) x (221 + 1) nearly equal to 177.6 m s output frequency = f ch / (2 x 8 x (t1dr register value + 1)) = 10 mhz / (16 x 221 + 1)) nearly equal to 2.815 khz table 8.1-2 timer 1 interval time and square wave output range in the 8-bit mode count clock cycle interval time square wave output range (hz) internal count clock 2t inst 2t inst to 2 9 t inst 1/(2 2 t inst ) to 1/(2 10 t inst ) 32t inst 2 5 t inst to 2 13 t inst 1/(2 6 t inst ) to 1/(2 14 t inst ) 512t inst 2 9 t inst to 2 17 t inst 1/(2 10 t inst ) to 1/(2 18 t inst ) external clock 1t ext 1t ext to 2 8 t ext 1/(2t ext ) to 1/(2 9 t ext ) table 8.1-3 timer 2 interval time and square wave output range in the 8-bit mode count clock cycle interval time internal count clock 2t inst 2t inst to 2 9 t inst 32t inst 2 5 t inst to 2 13 t inst 512t inst 2 9 t inst to 2 17 t inst table 8.1-4 interval time and square wave output range in the 16-bit mode count clock cycle interval time square wave output range (hz) internal count clock 2t inst 2t inst to 2 17 t inst 1/(2 2 t inst ) to 1/(2 18 t inst ) 32t inst 2 5 t inst to 2 21 t inst 1/(2 6 t inst ) to 1/(2 22 t inst ) 512t inst 2 9 t inst to 2 25 t inst 1/(2 10 t inst ) to 1/(2 26 t inst ) external clock 1t ext 1t ext to 2 16 t ext 1/(2t ext ) to 1/(2 17 t ext ) t inst : instruction cycle (influenced by the clock mode, etc.) t ext : external clock cycle (1 t ext greater than or equal to 2 t inst )
202 chapter 8 8/16-bit timer/counter n counter function the counter function counts how many times it detects the falling edge of the external clock that is input to the external pin. for the 8/16-bit counter, the ec pin is the external clock input pin. since the external clock can be selected only for timer 1, the counter function operates for timer 1 in the 8-bit mode or for the 16-bit mode. ? the counter counts up according to the external clock and, if the counter value is equal to the setting value, generates an interrupt request and reverses the output level of the square wave output pin. ? in the 8-bit mode, timer 1 can count up to 2 8 . ? in the 16-bit mode, the timer can count up to 2 16 . ? the counter can be used in the same way as for the interval timer function if an external clock with a fixed cycle is input.
203 8.2 configuration of the 8/16-bit timer/counter 8.2 configuration of the 8/16-bit timer/counter the 8/16-bit timer/counter consists of the following five blocks: ? count clock selectors 1 and 2 ? counter circuits 1 and 2 ? square wave output control circuit ? timer data registers (t1dr, t2dr) ? timer control registers (t1cr, t2cr) n block diagram of the 8/16-bit timer/counter figure 8.2-1 block diagram of the 8/16-bit timer/counter internal data bus str1 tc10 tc11 to10 to11 t1ie t1if timer control register t1cr stp1 terminal control/output initialization square wave output control circuit 1 pin 8-bit counter comparator timer data register (t1dr) 1t inst count clock selector 1 interrupt request irqe output enable signal p20/to1 timer data register (t2dr) comparator 8-bit counter count clock selector 2 str2 tc20 tc21 to20 to21 t2ie t2if timer control register t2cr stp2 counter circuit 1 counter circuit 2 t1dr, t2dr write t2dr read 1 t inst r, s q t.ff 2 2 t1dr read t inst : instruction cycle pin p84/ec 2 load comparator data latch eq load comparator data latch eq ck clr ck clr co ck q ck to2 to1 t.ff terminal control/output initialization square wave output control circuit 2 r,s pin p23/to2
204 chapter 8 8/16-bit timer/counter m count clock selectors 1 and 2 the count clock selectors 1 and 2 select the internal count clock. for timer 1 in the 8-bit mode or for the 16-bit mode, three types of internal clocks and one type of external clock can be selected. for timer 2 in the 8-bit mode, only three types of internal clocks can be selected. m counter circuits 1 and 2 each of the counter circuits 1 and 2 consists of the 8-bit counter, comparator, comparator data latch, and data registers (t1dr, t2dr). the 8-bit counter counts up according to the selected count clock. the comparator compares the counter value and the comparator data latch value and, if there is a match, clears the counter and sets (loads) the data register value in the comparator data latch. in the 8-bit mode, the counter circuits 1 and 2 operate independently as timers 1 and 2. in the 16-bit mode, the counter circuits 1 and 2 operate as one 16-bit counter with the former as the lower 8-bit and the latter as the upper 8-bit. m square wave output control circuit if the comparator detects a match in the 8-bit or 16-bit mode, this circuit generates an interrupt request. if the square wave output is enabled at this time, a corresponding output control circuit reverses the output of the square wave output pin. additionally, the square wave output can be initialized either to the "l" or "h" level. m timer data registers (t1dr, t2dr) while writing, these registers are used to set data to be compared with the values in the 8-bit counters. while reading, the current counter values in the counters are read. m timer control registers (t1cr, t2cr) select a function, enable and disable the operation, control an interrupt, and check the status. m interrupt of the 8/16-bit timer/counter irqe: generates an irqe interrupt request if the interrupt request output is enabled (t1cr: t1ie=1 for timer 1 in the 8-bit mode or for the 16-bit mode or t2cr: t2ie=1 for timer 2 in the 8-bit mode) when the counter value becomes equal to the value in the data register either in the interval timer or the counter function mode.
205 8.3 pins of the 8/16-bit timer/counter 8.3 pins of the 8/16-bit timer/counter this section describes the pins related to the 8/16-bit timer/counter and shows the block diagram of the pins. n pins related to the 8/16-bit timer/counter the pins related to the 8/16-bit timer/counter are p84/ec, p20/t01, and p23/t02. m p84/ec pin the p84/ec pin functions to operate as the general-purpose input port (p84), the 8/16-bit timer external clock input pin (ec), and the 16-bit timer input pin. ec: counts the clock that is input to this pin if an external clock input is selected (t1cr:tc11, tc10=11) for timer 1 in the 8-bit mode or for the 16-bit mode. m p20/t01 and p23/t02 pins the p20/t01 and p23/t02 pins function to operate as the general-purpose input port (p20, 23) and the square wave output pin for the timer (t01, 02). t01: outputs square waves from this pin for timer 1 in the 8-bit mode or for the 16-bit mode. the p20/t01 pin automatically becomes the output pin regardless of the output latch value and operates as the t01 pin if the square wave output is enabled (t2cr: t011, t010=00 b ). t02: outputs square waves from this pin for timer 2 in the 8-bit mode. the p23/t02 pin automatically becomes the output pin regardless of the output latch value and operates as the t02 pin if the square wave output is enabled (t2cr: t021, t020=00 b ).
206 chapter 8 8/16-bit timer/counter n block diagram of the pins related to the 8/16-bit timer/counter figure 8.3-1 block diagram of the pins related to the 8/16-bit timer/counter pin p-ch n-ch pdr read pdr write ddr write output latch stop/watch mode (spl=1) from the resource output from the resource output enable pdr (port data register) ddr internal data bus (port direction register) stop/watch mode ddr read ddr (port direction register) p20/to1 p23/to2 to ec input p84/ec pin pdr read pdr (port data register) internal data bus spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
207 8.4 registers of the 8/16-bit timer/counter 8.4 registers of the 8/16-bit timer/counter this section describes the registers related to the 8/16-bit timer/counter. n registers related to the 8/16-bit timer/counter figure 8.4-1 registers related to the 8/16-bit timer/counter bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t1cr (timer 1 control register) to10 tc11 stp1 str1 tc10 t1ie t1if to11 address 001b h initial value x00000x0 b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t2cr (timer 2 control register) to20 tc21 stp2 str2 tc20 t2ie t2if to21 address 001a h initial value x00000x0 b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t1dr (timer 1 data register) address 001d h initial value xxxxxxxx b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t2dr (timer 2 data register) address 001c h initial value xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled r : read only
208 chapter 8 8/16-bit timer/counter 8.4.1 timer 1 control register (t1cr) the timer 1 control register (t1cr) selects a function, enables or disables an operation, controls an interrupt, and checks the status of timer 1 in the 8-bit mode or of the 16-bit mode of the 8/16-bit timer/counter. to use only timer 1 in the 8-bit mode, you must also initialize the timer 2 control register (t2cr). n timer 1 control register (t1cr) figure 8.4-2 timer 1 control register (t1cr) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001b h address x00000x0 b initial value t1if t1ie to10 tc10 stp1 str1 r/w to11 r/w r/w stp1 0 1 timer stop bit continues the operation without clearing the counter. suspends the counter operation. tc11 tc11 0 0 1 1 tc10 0 1 0 1 count clock select bit 2 tinst 32 tinst 512 tinst external clock tinst: instruction cycle r/w str1 0 1 timer start bit stops the counter operation. clears the counter and starts the operation. *1 : the square wave output terminal has a level corresponding to the defined data if str1 is set to "0". tiif clears this bit no change and no influence on others write interrupt request flag bit read no counter match occurs. 0 1 a counter match occurs. r/w r/w r/w interrupt request enable bit disables the interrupt request output. enables the interrupt request output. to11 0 0 1 1 to10 0 1 0 1 square wave output control bit used as a general-purpose port (p20) set to data that makes the square wave output "l" set to data that makes the square wave output "h" outputs a level corresponding to the defined data to the square wave output terminal (t01). *1 t1ie 0 1 r/w : read/write enabled x : undefined : initial value
209 8.4 registers of the 8/16-bit timer/counter table 8.4-1 functions of the bits in the timer 1 control register (t1cr) bit name function bit 7 t1if: interrupt request flag bit ? in the 8-bit mode set to "1" if timer 1 has the counter value that matches the timer 1 data register (t1dr) setting value (comparator data latch). ? in the 16-bit mode set to "1" if timers 1 and 2 have counter values that match the t1dr and t2dr setting values, respectively. setting this bit and the interrupt request enable bit (t1ie) to "1" outputs an interrupt request. cleared to "0" while writing. setting this bit to "1" does not affect it and causes no change. bit 6 t1ie: interrupt request enable bit ? enables or disables the interrupt request output to the cpu. setting this bit and the interrupt request flag bit (t1if) to "1" outputs an interrupt request. bit 5 bit 4 t011, t010: square wave output control bits ? setting these bits to "00 b " makes the t20/t01 pin a general-purpose port (p20). setting these bits to any other value makes it a square wave output pin (t01). ? writing "01 b " or "10 b " in these bits sets the initialization data in the square wave output control circuit but does not output it to the t01 pin. ? if these bits are set to "11 b " and the timer is stopped (str1=0), the t01 pin is set to a level corresponding to the initialization data. bit 3 bit 2 tc11, tc10: clock source select bit ? selects the count clock to be supplied to the counter. ? selects one of the three internal clocks and one external clock. setting these bits to "11 b " selects the external clock input and the operation as the counter function. note: selecting the external clock input (tc11, tc100=11 b) uses the input of the p84/ec pin as the clock. bit 1 stp1: timer stop bit ? suspends the counter. writing "1" in this bit suspends the counter operation. while the timer is started (str1=1), writing "0" causes the counter to continue the operation. bit 0 str1: timer start bit ? starts or stops the counter. ? changing this bit from "0" to "1" clears the counter. if the timer operation is continued (stp1=0) at this time, the counter starts the operation and counts up using the selected count clock. writing "0" in this bit stops the counter operation. ? in the 16-bit mode, starting the timer (stp1=0 --> 1) clears timer 1 and 2 counters.
210 chapter 8 8/16-bit timer/counter note: to use only timer 1 of the 8/16-bit timer/counter in the 8-bit mode and to prevent a malfunction, set a value other than "11b" in the timer count clock select bits (t2cr: tc21, tc20) in the timer 2 control register.
211 8.4 registers of the 8/16-bit timer/counter 8.4.2 timer 2 control register (t2cr) the timer 2 control register (t2cr) selects a function, enables or disables an operation, controls an interrupt, and checks the status for timer 2 in the 8-bit mode of the 8/16-bit timer/counter. to use timer 2 in the 16-bit mode, the t2cr register must also be set although the timer 1 control register (t1cr) is used to control timer 2. n timer 2 control register (t2cr) figure 8.4-3 timer 2 control register (t2cr) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001a h x00000x0 b t2if t2ie to20 tc20 stp2 str2 r/w to21 r/w r/w stp2 0 1 tc21 tc21 0 0 1 1 tc20 0 1 0 1 r/w str2 0 1 tiif 0 1 r/w r/w r/w to21 0 0 1 1 to20 0 1 0 1 t1ie 0 1 address initial value timer start bit stops the counter operation. clears the counter and starts the operation. timer stop bit continues the operation without clearing the counter. suspends the counter operation. square wave output control bit used as a general-purpose port (p23) set to data that makes the square wave output "l" set to data that makes the square wave output "h" outputs a level corresponding to the defined data to the square wave output terminal (t02). *1 no change and no influence on others write interrupt request flag bit read no counter match occurs. *1 : the square wave output terminal has a level corresponding to the defined data if str2 is set to "0". count clock select bit 2 tinst 32 tinst 512 tinst 16-bit mode tinst: instruction cycle interrupt request enable bit disables the interrupt request output. enables the interrupt request output. a counter match occurs. clears this bit r/w : read/write enabled x : undefined : initial value
212 chapter 8 8/16-bit timer/counter table 8.4-2 functions of the bits in the timer 2 control register (t2cr) bit name function bit 7 t2if: interrupt request flag bit set to "1" if timer 2 has a counter value matching the timer 2 data register (t2dr) setting value (comparator data latch). ? setting this bit and the interrupt request enable bit (t2ie) to "1" outputs an interrupt request. ? cleared to "0" while writing. setting this bit to "1" does not affect it and causes no change. note: in the 16-bit mode, the t1if bit becomes valid and the t2if bit becomes irrelevant to the operation. bit 6 t2ie: interrupt request enable bit ? enables or disables the interrupt request output to the cpu. ? setting this bit and the interrupt request flag bit (t2if) to "1" outputs an interrupt request. note: in the 16-bit mode, the t1ie bit becomes valid and the t2ie bit becomes irrelevant to the operation. bit 5 bit 4 t021, t020: square wave output control bits setting these bits to "00 b " makes the t23/t02 pin a general- purpose port (p23). setting these bits to any other value makes it a square wave output pin (t02). if the hclk output is enabled at the same time, the square wave output (t02) is prioritized. ? writing "01 b " or "10 b " in these bits sets the initialization data in the square wave output control circuit but does not output it to the t02 pin. ? if these bits are set to "11 b " and the timer is stopped (str1=0), the t02 pin is set to a level corresponding to the initialization data. bit 3 bit 2 tc21, tc20: clock source select bit ? selects the count clock to be supplied to the counter. ? selects one of the three internal clocks. ? setting these bits to "11 b " selects the 16-bit mode. note: in the 16-bit mode, the tc11 and tc10 bits becomes valid and the tc21 and tc20 bits only select the 16-bit mode. bit 1 stp2: timer stop bit ? suspends the counter. ? writing "1" in this bit suspends the counter operation. while the timer is started (str2=1), writing "0" causes the counter to continue the operation. note: in the 16-bit mode, the stp1 bit becomes valid and the stp2 bit becomes irrelevant to the operation.
213 8.4 registers of the 8/16-bit timer/counter note: to use the operation in the 16-bit mode, write "11 b " in the tc21 and tc20 bits and then perform control using the t1cr register. bit 0 str2: timer start bit ? starts or stops the counter. ? changing this bit from "0" to "1" clears the counter. if the timer operation is continued (stp2=0) at this time, the counter starts the operation and counts up using the selected count clock. writing "0" in this bit stops the counter operation. note: in the 16-bit mode, the str1 bit becomes valid and the str2 bit becomes irrelevant to the operation. table 8.4-2 functions of the bits in the timer 2 control register (t2cr) (continued) bit name function
214 chapter 8 8/16-bit timer/counter 8.4.3 timer 1 data register (t1dr) the timer 1 data register (t1dr) is used to set an interval timer value (in the interval timer function mode) or a counter value (in the counter function mode) for timer 1 in the 8-bit mode or for the lower 8 bits in the 16-bit mode of the 8/16-bit timer/counter as well as read the counter value. n timer 1 data register (t1dr) the value in this register is compared with the counter value. reading this register reads the current counter value. the value in this register cannot be read. figure 8.4-4 "timer 1 data register (t1dr)" shows the bit configuration of the timer 1 data register. figure 8.4-4 timer 1 data register (t1dr) m in the 8-bit mode (timer 1) the value in this register is compared with the counter value. this register is set to an interval time value in the interval timer function mode or a count value to be detected in the counter function mode. enabling the count operation (t1cr: str1=0 --> 1, stp1=0) sets (loads) the t1dr register value in the comparator data latch and starts the count-up. if the comparator data latch value and the counter value match due to the count-up, the t1dr register value is reset in the comparator data latch, the counter is cleared, and the count operation is continued. the comparator data latch is reset if a match is detected. thus, a value written in the t1dr register while the counter operates becomes valid in the next cycle (after a match is detected) and thereafter. you can calculate the value in the t1dr register in the interval timer mode as follows. note that the instruction cycle is influenced by the clock mode or the gear function. t1dr register value = interval time / (count clock cycle x instruction cycle) -1 r/w r/w r/w r/w r/w r/w r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001d h address xxxxxxxx b initial value r/w : read/write enabled x : undefined
215 8.4 registers of the 8/16-bit timer/counter m in the 16-bit mode the value in this register is compared with the lower 8 bits of the counter value of the 16-bit timer. this register is set to the lower 8 bits of the interval time in the interval timer function mode or the lower 8 bits of a count value to be detected in the counter function mode. the t1dr register value is loaded to the lower 8 bits of the comparator data latch when the count operation is started or when a match with the 16-bit counter value is detected. a value written in the t1dr register while the 16-bit counter operates becomes valid when a match is detected. for the setting values in the t1dr register in the interval timer function mode, see section 8.4.4 "timer 2 data register (t2dr)".
216 chapter 8 8/16-bit timer/counter 8.4.4 timer 2 data register (t2dr) the timer 2 data register (t2dr) is used to set an interval timer value (in the interval timer function mode) or a counter value (in the counter function mode) for timer 2 in the 8-bit mode or for the upper 8 bits in the 16-bit mode of the 8/16-bit timer/counter and is also used to read the counter value. n timer 2 data register (t2dr) the value in this register is compared with the counter value. reading this register reads the current counter value. the value in this register cannot be read. figure 8.4-5 "timer 2 data register (t2dr)" shows the bit configuration of the timer 2 data register. figure 8.4-5 timer 2 data register (t2dr) m in the 8-bit mode (timer 2) the value in this register is compared with the timer 2 counter value. this register is set to an interval time value in the interval timer function mode or a count value to be detected in the counter function mode. the t2dr register is reset (loaded) to the comparator data latch when the counter operation is started or a match with the counter value is detected. a value written in the t2dr register while the counter operates becomes valid in the next cycle (after a match is detected) and thereafter. the t2dr register in the interval timer mode can be calculated as follows. note that the instruction cycle is affected by the clock mode or the gear function. t2dr register value = interval time / (count clock cycle x instruction cycle) -1 r/w r/w r/w r/w r/w r/w r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001c h address xxxxxxxx b initial value r/w : read/write enabled x : undefined
217 8.4 registers of the 8/16-bit timer/counter m in the 16-bit mode the value in this register is compared with the upper 8 bits of the counter value of the 16-bit timer. this register is set to the upper 8 bits of interval time in the interval timer function mode or the upper 8 bits of a count value to be detected in the counter function mode. the t2dr register is loaded to the upper 8 bits of the comparator data latch when the count operation is started or when a match with the 16-bit counter value is detected. a value written in the t2dr register while the 16-bit counter operates becomes valid when a match is detected. the count operation is controlled in the 16-bit mode using the timer 1 control register (t1cr). you can calculate the values in the t1dr and t2dr registers in the interval timer mode as follows. note that the instruction cycle is influenced by the clock mode or the gear function. 16-bit data value = interval time / (count clock cycle x instruction cycle) -1 the upper and lower 8 bits of the 16-bit data value are set to the t2dr and t1dr registers, respectively.
218 chapter 8 8/16-bit timer/counter 8.5 8/16-bit timer/counter interrupts an interrupt of the 8/16-bit timer/counter is caused by a match of the data register setting value and the count value both in the interval timer and counter operation modes. the 8/16-bit timer/counter generates an irqe as an interrupt request. n 8/16-bit timer/counter interrupts table 8.5-1 "interrupt request flag bit and interrupt cause of the 8/16-bit timer/counter" shows the relationship between an interrupt request flag bit, an interrupt request output enable bit, and an interrupt cause of the 8/16-bit timer/counter. an interrupt request of the 8/16-bit timer/counter is generated by timers 1 and 2 independently in the 8-bit mode and by timer 1 in the 16-bit mode. however, the basic operation is the same in both modes. this section describes the interrupt operation of timer 1 in the 8-bit mode. m interrupt operation of timer 1 in the 8-bit mode if the counter counts up from "00 h " according to the selected count clock and matches the setting value in the comparator data latch corresponding to the timer data register (t1dr), the interrupt request flag bit (t1cr: t1if) is set to "1". if the interrupt request flag bit is set to enabled (t1cr: t1if=1) at this time, an interrupt request (irqe) occurs in the cpu. use the interrupt processing routine to write "0" in the t1if bit and clear the interrupt request. the t1if bit is set to "1" regardless of the value in the t1ie bit if the counter value and the setting value match. since timers 1 and 2 operate independently in the 8-bit mode and generate the same interrupt request (irqe), the software may have to evaluate the interrupt request flag bit. note: if the counter value and the t1dr register value match and the counter is stopped (t1cr: str1=0) at the same time, the t1if bit is not set. while the t1if bit is "1", setting the t1if bit from disabled to enabled (0 --> 1) immediately causes an interrupt request. table 8.5-1 interrupt request flag bit and interrupt cause of the 8/16-bit timer/counter 8-bit mode 16-bit mode timer 1 timer 2 timers 1+2 interrupt request flag bit t1cr:t1if t2cr:t2if t1cr:t1if interrupt request enable bit t1cr:t1ie t2cr:t2ie t1cr:t1ie interrupt cause a match of the t1dr setting value and the 8-bit counter value a match of the t2dr setting value and the 8-bit counter value a match of the t1dr and t2dr setting value and the 16-bit counter value
219 8.5 8/16-bit timer/counter interrupts n register related to the interrupts of the 8/16-bit timer/counter and the vector table for the interrupt operation, see section 3.4.2 "interrupt processing during". table 8.5-2 register related to the interrupts of the 8/16-bit timer/counter and the vector table interrupt name interrupt level setting register vector table address register bit to be set upper lower 8/16-bit timer/counter irqe ilr4 (007e h ) le1 (bit 5) le0 (bit 4) ffde h ffdf h
220 chapter 8 8/16-bit timer/counter 8.6 operation of the interval timer function this section describes the operation of the interval timer function of the 8/16-bit timer/ counter. n operation of the interval timer function m in the 8-bit mode to use timer 1 in the 8-bit mode as the interval timer function, the setting shown in figure 8.6-1 "setting the interval timer function (timer 1)" must be made. figure 8.6-1 setting the interval timer function (timer 1) to use timer 2 in the 8-bit mode as the interval timer function, the setting shown in figure 8.6-2 "setting the interval timer function (timer 2)" must be made. figure 8.6-2 setting the interval timer function (timer 2) if the counter is started in the 8-bit mode, the counter starts counting up from "00 h " at every rising edge of the selected clock. if the counter value matches the value in the data register (comparator data latch), the interrupt request flag bit (t1cr: t1if or t2if) is set to "1" and the counter starts counting from "00 h ". if the output of the square wave output control circuit is reversed and the square wave output is enabled (t011, t010, and t021, t020=other than 00b), a corresponding timer output pin outputs square waves. timers 1 and 2 correspond to the t01 and t02 pins, respectively. figure 8.6-3 "operation of the interval timer function in the 8-bit mode (timer 1)" shows the operation of the interval timer function in the 8-bit mode. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t1cr : used bit : unused bit 0 : set to 0 t1dr set to the interval time (comparison value) to10 tc11 stp1 str1 tc10 t1ie t1if to11 other than 11 other than 11 t2cr to20 tc21 stp2 str2 tc20 t2ie t2if to21 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t2cr t2dr to20 tc21 stp2 str2 tc20 t2ie t2if to21 : used bit 0 : set to 0 set to the interval time (comparison value) other than 11
221 8.6 operation of the interval timer function figure 8.6-3 operation of the interval timer function in the 8-bit mode (timer 1) m in the 16-bit mode to use the interval timer function in the 16-bit mode, the setting shown in figure 8.6-4 "setting the interval timer function (in the 16-bit mode)" must be made. figure 8.6-4 setting the interval timer function (in the 16-bit mode) although the timer 1 control register (t1cr) is used to control the timer in the 16-bit mode, the timer 2 control register (t2cr) must be initialized. the data register is set to a 16-bit value with the t2dr and t1dr registers as upper and lower 8 bits, which is then compared with the 16-bit counter value. when the counter is cleared, all the 16 bits are cleared at the same time. other operations in the 16-bit mode are the same as timer 1 in the 8-bit mode. 80 h 00 h changing the t1dr value (e0 h -> ff h ) (*1) time comparison value (e0 h ) comparison value (ff h ) counter value t1dr value (e0 h ) t1if bit to1 terminal counter clear (*2) t1str bit (t1stp=0) cleared by the program match match match start *1: a value rewritten in the data register during the counter operation is valid in the next cycle and thereafter. *2: when the counter is started and when a match is detected, the counter is cleared and the data register setting value is loaded to the comparator data latch. e0 h ff h t2cr : used bit : unused bit 1 : set to 1 0 : set to 0 t1dr t2dr set to the lower 8 bits of the interval time set to the upper 8 bits of the interval time bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t1cr to10 tc11 stp1 str1 tc10 t1ie t1if to11 to20 tc21 stp2 str2 tc20 t2ie t2if to21 00 1 1 other than 11
222 chapter 8 8/16-bit timer/counter 8.7 operation of the counter function this section describes the operation of the counter function of the 8/16-bit timer/ counter. n operation of the counter function m in the 8-bit mode to use timer 1 in the 8-bit mode as the counter function, the setting shown in figure 8.7-1 "setting the counter function (in the 8-bit mode)" must be made. figure 8.7-1 setting the counter function (in the 8-bit mode) the counter function in the 8-bit mode operates in the same way as the interval timer function (timer 1 in the 8-bit mode) except that the external clock is used instead of the internal clock. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t1cr#1 : used bit : unused bit 0 : set to 0 t1dr#1 set to the counter value to be compared to10 tc11 stp1 str1 tc10 t1ie t1if to11 ddr4 0 t2cr#2 to20 tc21 stp2 str2 tc20 t2ie t2if to21 other than 11
223 8.7 operation of the counter function m in the 16-bit mode to use the counter function in the 16-bit mode, the setting shown in figure 8.7-2 "setting the counter function (in the 16-bit mode)" must be made. figure 8.7-2 setting the counter function (in the 16-bit mode) the counter function in the 16-bit mode operates in the same way as an interval timer function (in the 16-bit mode) except that the external clock is used instead of the internal clock. figure 8.7-3 "operation of the counter function in the 16-bit mode" shows the operation of the counter function in the 16-bit mode. t2cr#2 t1dr#1 t2dr#2 set to the lower 8 bits of the counter value to be compared set to the upper 8 bits of the counter value to be compared t1cr#1 to10 tc11 stp1 str1 tc10 t1ie t1if to11 to20 tc21 stp2 str2 tc20 t2ie t2if to21 00 1 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr4 0 : used bit : unused bit 1 : set to 1 0 : set to 0
224 chapter 8 8/16-bit timer/counter figure 8.7-3 operation of the counter function in the 16-bit mode note: when reading a value in the operating counter in the 16-bit mode, always read it twice and check whether it is an appropriate value before using it. cleared by the program t1if register external clock counter clear str1 bit (stp1=0) counter value 0000 h 0001 h 0002 h 0003 h 1388 h 0000 h 0001 h t1dr register (*1) (lower 8-bit setting value) 34 h 88 h t2dr register (*1) (upper 8-bit setting value) 12 h 13 h *1: may be set to a pre-specified value at pre-specified timing. when the counter is started or when a match is detected, the data register setting value is loaded to the comparator data latch. at this time, the counter is cleared. data setting (1234 h ) comparator data latch 1 (lower 8-bit comparison value) 34 h 88 h comparator data latch 2 (upper 8-bit comparison value) 12 h 13 h load load
225 8.8 operation of the square wave output initial setting function 8.8 operation of the square wave output initial setting function the square wave output can be set to a pre-specified initial value using the timer 1 control registers (t1cr, t1cr, t2cr, t2cr). n operation of the square wave output initial setting function although this section describes only the operation of timer 1, the operation of timer 2 is the same. the square wave output can be set to a pre-specified initial value using the program only if the timer operation is stopped (t1cr: str1=0). figure 8.8-1 "square wave output initial setting equivalent circuit" shows the initial setting equivalent circuit in the square wave output control circuit. make the initial setting as shown in table 8.8-1 "making the initial setting of the square wave output (t1cr register)". the square wave output operation at this time is shown in figure 8.8-2 "initial setting operation of the square wave output". figure 8.8-1 square wave output initial setting equivalent circuit dq dq q dq write strobe signal str2 to21 to20 level latch level latch q q r r r dq q r pin p-ch n-ch p20 q s r reset signal comparator match signal output latch general-purpose port stop/watch mode (spl=1) table 8.8-1 making the initial setting of the square wave output (t1cr register) procedure setting and operation (1) to set the square wave output pin (t01) to the "l" level, write "01 b " in the square wave output control bits (t1cr: t011, t010) and then write "11 b ". in addition, to set it to the "h" level, write "10 b " and "11 b " in this order. note: until "11 b " is written, only the level latch stores the value and the t01 pin has the current or previous level.
226 chapter 8 8/16-bit timer/counter figure 8.8-2 initial setting operation of the square wave output (2) writing "11 b " in the square wave output control bits (t011, t010) to stop the timer operation (str1=0) outputs a level (initial value) corresponding to a value in the level latch to the t01 pin. (3) setting the timer start bit (str1=1) starts the counter operation. (4) the square wave output is reversed when the counter value and the data register setting value match. table 8.8-1 making the initial setting of the square wave output (t1cr register) procedure setting and operation timer *2 previous square wave output setting value port *1 p20/t01 status square wave output *1: setting the t011 and t010 bits in the t1cr register to "00 b " makes the t20/t01 pin a general-purpose port (p20). *2: setting either the t011 or t010 bit to "1" makes the t20/t01 pin a square wave output pin (t01).
227 8.9 operation of stopping and restarting the 8/16-bit timer/counter 8.9 operation of stopping and restarting the 8/16-bit timer/ counter this section describes the operation of stopping and restarting the 8/16-bit timer/ counter. n operation of stopping and restarting the 8/16-bit timer/counter although this section describes only the operation of timer 1, the operation of timer 2 is the same. the timer stop bit (stp1) and the timer start bit (str1) in the timer 1 control register are used to stop and restart timer 1. to clear the counter and start the count operation, set the stp1 and str1 bits to "01 b " when the str1 bit is "0". the timer is cleared and the count operation is started at a rising edge of the str1 bit. suspending the timer and restarting the count operation without clearing the counter: to suspend the count operation, set the stp1 and str1 bits to "11 b ". to restart the count operation without clearing the counter, set the stp1 and str1 bits to "01 b ". table 8.9-1 "stopping and restarting the timer" shows timer statuses depending on the stp1 and str1 bits and the timer operation when it is started (stp1, str1=01b) in each of these statuses table 8.9-1 stopping and restarting the timer stp1 (stp2) str1 (str2) timer status timer operation when it is started (stp1, str1=01 b ) in the status shown on the left 0 0 count operation stopped clears the counter and starts the count operation. 0 1 count operation in progress continues the count operation. 1 0 count operation stopped clears the counter and starts the count operation. 1 1 count operation suspended restarts the count operation without clearing the counter
228 chapter 8 8/16-bit timer/counter 8.10 status of the 8/16-bit timer/counter in each mode this section describes the operations of switching to the sleep and stop modes and receiving a suspend request during the operation of the 8/16-bit timer/counter. n operation in the subclock and standby modes and when the counter is suspended figure 8.10-1 "operation in the subclock and standby modes and when the counter is suspended" shows the counter value statuses upon switching to the sleep and stop modes and receiving a suspend request while the interval timer or counter function is operating. in the stop mode, the counter stops, maintaining the value. if the stop mode is cleared by an external interrupt, the counter starts counting from the maintained value. therefore, the initial interval time and the external clock count cannot be correct values. after the stop mode is cleared, initialize the 8/16-bit timer/counter again. the operations of switching to and clearing the watch mode (stbc: tmd=1) is the same as the operation of switching to and clearing the stop mode. the watch mode is cleared by a watch interrupt and an external interrupt. if the counter is suspended (t1stp=1), the counter stops, maintaining the value. if the operation is continued (t1stp=0), the count operation is restarted. figure 8.10-1 operation in the subclock and standby modes and when the counter is suspended time counter value 0000 h match match match counter clear match match str1 bit t1if bit (t1ie bit) t01 terminal slp bit (stbc register) stp bit (stbc register) * sleep sleep cleared by irq5 stop external interrupt stp1 bit suspend cleared by the program data register setting value start *1: if the terminal status specification bit in the standby control register (stbc: spl) is set to "1" and the t01 terminal is not pulled up (optional), the t01 terminal in the stop mode has a high impedance. if the spl bit is "0", the value immediately before entering the stop mode is maintained.
229 8.11 notes on using the 8/16-bit timer/counter 8.11 notes on using the 8/16-bit timer/counter this section describes the precautions when using the 8/16-bit timer/counter. n notes on using the 8/16-bit timer/counter m precautions when stopping the timer although this section describes only the operation of timer 1, the operation of timer 2 is the same. if the stp1 bit is used to suspend the timer and the input clock is the "h" level, the counter value is incremented by "1". if, after the timer is suspended, "00 b " is written into the stp1 and str1 bits at the same time and the input clock is the "l" level, the counter value is sometimes incremented by "1". if the stp1 bit is used to suspend the timer, read the counter value and then write "0" in the str1 bit. figure 8.11-1 operation when the timer stop bit is used m error the counter start by the program and the count-up start by the selected count clock are asynchronous. thus, an error of one instruction cycle shorter at the maximum may exist in the time elapsing until the count value and the setting data match. figure 8.11-2 "error until the count operation is started" shows an error until the count operation is started. 01 h 01 02 h 11 00 suspend stop input clock to the timer (ec, internal clock) 01 h 02 h 01 11 suspend stop counter value stp1 and str1 bits (t1cr register) if the input clock is "l" if the input clock is "h" 03 h 04 h 00
230 chapter 8 8/16-bit timer/counter figure 8.11-2 error until the count operation is started m using one 8-bit channel to use only timer 1 of the 8/16-bit timer/counter in the 8-bit mode and to prevent a malfunction, set a value other than "11 b " in the timer count clock select bits (t2cr: tc21, tc20) in the timer 2 control register. m precautions when making a setting in a program ? to use the 8/16-bit timer/counter in the 16-bit mode, set "11 b " in the count clock select bits in the timer 2 control register (t2cr: tc21, tc20) and "00 b " in the unused bits of bits 5 and 4 (t2cr: t021, t020). ? when reading a value in the operating counter in the 16-bit mode, read it twice and check whether it is an appropriate value before using. ? initializing the square wave output while the timer is operating (t1cr: str1=1) does not change the output value. the output is initialized while the timer operation is stopped. ? if the interrupt request flag bits (t1cr: t1if, t2cr: t2if) are "1" and the interrupt request enable bits (t1cr: t1ie=1, t2cr: t2ie=1) are enabled, a recovery from an interrupt cannot be made. always clear the interrupt request flag bit. ? if the timer start bits are used to stop the counter operation (t1cr: str1=0, t2cr: str2=0) and an interrupt cause occurs at the same time, the interrupt request flag bits (t1cr: t1if, t2cr: t2if) are not set. counter value count clock 23 0 14 counter started one cycle error setting value: cycle of count 0
231 8.11 notes on using the 8/16-bit timer/counter m writing a value to the data register in the 16-bit mode if a word write instruction is used to write a value to the t1dr and t2dr registers in the 16-bit mode, the cpu sets the data by splitting it into upper and lower 8 bits as shown in table 8.11-1 "word data transfer operation", "word data transfer operation". thus, if an interrupt request occurs while executing a word write instruction, only the lower 8-bit data will be valid and the upper 8-bit data may not be valid until the next interrupt request is made. to change the interval time during the timer operation, write data to the timer data registers (t1dr, t2dr) three cycles before an interrupt request occurs (see figure 8.11-3 "internal bus operation when the "movw dir, a" instruction is executed"). figure 8.11-3 internal bus operation when the "movw dir, a" instruction is executed table 8.11-1 word data transfer operation instruction cycle count address bus data bus rd wr movw a,dir 1 2 3 4 n+1 dir address dir+1 address n+2 dir data (upper) data (lower) next instruction 0 0 0 0 1 1 1 1 movw dir,a 1 2 3 4 n+1 dir+1 address dir address n+2 dir data (lower) data (upper) next instruction 0 1 1 0 1 0 0 1 cycle 1 lower data set address bus n+1 dir+1 address dir address n+2 data bus dir data (lower) data (upper) next instruction interrupt flag cycle 2 cycle 3 cycle 4 upper data set three cycles
232 chapter 8 8/16-bit timer/counter
233 chapter 9 16-bit timer/counter this chapter describes the functions and operations of the 16-bit timer/counter. 9.1 "overview of the 16-bit timer/counter" 9.2 "configuration of the16-bit timer/counter" 9.3 "pin of the 16-bit timer/counter" 9.4 "registers of the 16-bit timer/counter" 9.5 "16-bit timer/counter interrupts" 9.6 "operation of the interval timer function" 9.7 "operation of the counter function" 9.8 "status of the 16-bit timer/counter in each mode" 9.9 "notes on using the 16-bit timer/counter" 9.10 "program example of the 16-bit timer/counter"
234 chapter 9 16-bit timer/counter 9.1 overview of the 16-bit timer/counter the 16-bit timer/counter has an interval timer function and a counter function. the interval timer function counts up in synchronization with the internal count clock (the oscillator frequency divided into four cycles). the counter function counts up by detecting a prespecified edge of a pulse that is input to the external pin. one of these functions can be selected. n interval timer function the interval timer function generates an interrupt at prespecified intervals. the 16-bit counter counts up from a setting value in synchronization with the internal count clock that divides the oscillator frequency into four cycles and generates an interrupt if the counter value overflows. ? interval timer operation up to an internal count clock times 2 16 is possible. ? use the interrupt processing routine to reset the interval time to generate an interrupt repeatedly. table 9.1-1 "range for interval time" shows the range for the interval time. the following shows an example of calculating the interval time. assuming the oscillator frequency (fc) to be 10 mhz and the timer counter register (tcr) to be 0000 h , calculate the interval time as follows: interval time = (4 / fc) x (2 16 - tcr register value) = (4 / 10 mhz) x 65536 early equal to 26.214 ms table 9.1-1 range for interval time internal count clock cycle interval time 1t ins 1t inst to 2 16 t inst t inst : instruction cycle (the oscillator frequency divided into four cycles)
235 9.1 overview of the 16-bit timer/counter n counter function the counter function detects the edge of a pulse that is input to the external pin (ec pin) and counts it. ? counts up every time a prespecified edge of the external input is detected and generates an interrupt if the counter value overflows. ? can detect the pulse width of the external input at a minimum of two instruction cycles. ? can be set to detect both rising and falling edges.
236 chapter 9 16-bit timer/counter 9.2 configuration of the 16-bit timer/counter the 16-bit timer/counter consists of the following five blocks: ? count clock selector ? edge detection circuit ? timer count register (tcr) ? timer control register (tmcr) ? lower 8-bit latch n block diagram of the 16-bit timer/counter figure 9.2-1 block diagram of the 16-bit timer/counter section m count clock selector selects the internal count clock (1 t inst ) in interval timer function mode. selects the output of the edge detection circuit in counter function mode. the selected signal will be used as the clock by the 16-bit counter (tcr register) to count up. m edge detection circuit operates in counter function mode and detects the rising and/or falling edges of a pulse that is input from the ec3 pin. internal data bus tcr tcs1 tcs0 tcef tcie tcs timer control register (tmcr) upper 8-bit tchr lower 8-bit tclr lower 8-bit latch tcr latch (falling) (rising) edge detection circuit p84/ec edge edge count clock selector select irqd count clock read data read data latching upon reading tchr *t inst : instruction cycle overflow pin 16-bit timer/counter interrupt counter clear * 1 t inst
237 9.2 configuration of the 16-bit timer/counter m timer count register (tcr) stores a value from which the 16-bit counter counts up. if the counter value overflows, the tmcr register interrupt request flag bit is set (tcef=1). m timer control register (tmcr) selects a function, enables and disables operation, controls interrupts, and checks the status. m lower 8-bit latch stores the lower 8 bits of the 16-bit counter when the tcr register upper 8-bit value (tchr) is read. since the lower 8-bit value of the counter (tclr) is read from this lower 8-bit latch, a correct 16-bit counter value can be read even while the counter is counting up. if, while the counter is operating, the lower 8-bit value is read before the upper 8-bit value, a correct value may not be read, depending on the counter carry. therefore, always use a word transfer instruction to read the tcr register. m interrupt related to the timer/counter irqd: generates an interrupt request if interrupt request output is enabled (tmcr: tcie = 1) when the counter value overflows either in interval timer or counter function mode.
238 chapter 9 16-bit timer/counter 9.3 pin of the 16-bit timer/counter this section describes the pin related to the 16-bit timer/counter and shows a block diagram. n pin related to the 16-bit timer/counter the pin related to the 16-bit timer/counter is the p84/ec pin. it functions both as a general- purpose input port (p84) and as an external pulse input pin for the counter (ec). ec: counts a prespecified edge of a pulse that is input to this pin in counter function mode. n block diagram of the pin related to the 16-bit timer/counter figure 9.3-1 block diagram of the pin related to the 16-bit timer/counter pin pdr read internal data bus pdr (port data register) to ec input p84/ec
239 9.4 registers of the 16-bit timer/counter 9.4 registers of the 16-bit timer/counter this section describes the registers related to the 16-bit timer/counter. n registers related to the 16-bit timer/counter figure 9.4-1 registers related to the 16-bit timer/counter bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address xx000000 b initial value r/w r/w r/w r/w r/w w tcs tcie tcef tcs0 tcs1 tcr - - 0 0 7 3 h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 4 h address 00000000 b initial value r rr rr r r r r/w r/w r/w r/w r/w r/w r/w r/w upper bits (tchr) --> while the counter is stopped --> while the counter is operating r rr rr r r r lower bits (tclr) 00000000 b 0 0 7 5 h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address initial value tmcr (timer control register) tcr (timer count register) r/w r/w r/w r/w r/w r/w r/w r/w --> while the counter is stopped --> while the counter is operating r/w : read/write enabled r : read only w : write only x : undefined
240 chapter 9 16-bit timer/counter 9.4.1 timer control register (tmcr) the timer control register (tmcr) selects a 16-bit timer/counter function (either the interval timer or counter function), sets the operating conditions, enables or disables operation, clears the counter, controls interrupts, and checks the status. n timer control register (tmcr) figure 9.4-2 timer control register (tmcr) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 3 h address xx000000 b initial value tcs1 tcef tcie tcs r/w tcr - - r/w r/w w tcef the bit is cleared. tcie 0 1 interrupt request enable bit disables interrupt request output. enables interrupt request output. write tcs0 tcr 0 1 tcs1 0 0 1 1 tcs0 0 1 0 1 counter operation mode select bit interval timer operation counter operation detects the falling edge of external input. detects the rising edge of external input. detects both edges of external input. r/w interrupt request flag bit read no counter overflow occurs. tcs 0 1 counter start bit disables or stops the count operation. enables or starts the count operation. counter clear bit clears the counter. there is no effect on operation. 0 1 a counter overflow occurs. no change and no influence on others r/w : read/write enabled w : write only x : undefined : initial value
241 9.4 registers of the 16-bit timer/counter note: when clearing the interrupt request flag bit (tmcr: tcef), do not overwrite the interrupt request enable bit (tmcr: tcie) at the same time. table 9.4-1 functions of the timer control register (tmcr) bits bit name function bit 7 bit 6 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 5 tcr: counter clear bit ? clears the timer count register (tcr). ? writing 0 to this bit clears the timer count register to 0000 h . writing 1 to this bit has no effect and has no effect on other bits. reference: if this bit is read, the value is always 1. bit 4 bit 3 tcs1, tcs0: counter operation mode select bits ? switches the interval timer and counter functions. setting these bits to 00 h selects the interval timer function that results in operation using the internal count clock. ? selecting an edge to be detected (falling, rising, or both) from the external count clock causes operation as a 16-bit counter. bit 2 tcef: interrupt request flag bit ? set to 1 if the counter overflows. ? setting this bit and the interrupt request enable bit (tcie) to 1 outputs an interrupt request. ? cleared to 0 for a write. setting this bit to 1 has no effect and does not affect operation. bit 1 tcie: interrupt request enable bit ? enables or disables interrupt request output to the cpu. ? setting this bit and the interrupt request flag bit (tcef) to 1 outputs an interrupt request. bit 0 tcs: starts or stops the counter. ? starts and stops the counter. ? writing 1 to this bit starts the count operation of the timer count register (tcr), which counts up according to the count clock. writing 0 to this bit stops the count operation, and the tcr retains the counter value.
242 chapter 9 16-bit timer/counter 9.4.2 16-bit timer count register (tcr) the timer count register (tcr) is a 16-bit up counter. the counter counts up from the setting value written in this register. n timer count register (tcr) figure 9.4-3 "16-bit timer count register (tcr)" shows the bit configuration of the 16-bit timer count register. figure 9.4-3 16-bit timer count register (tcr) both in the interval timer and counter function modes, set a counter initial value in this register while the counter operation is disabled (tmcr: tcs=0). when the counter operation is enabled (tcs=1), the counter counts up from the value written in this register. while the counter is stopped (tcs=0), the tcr register maintains its value. if the counter is cleared (tmcr:tcr=0), the tcr register (counter) becomes 0000 h . after the counter is cleared, writing a value in the tcr register sets the counter to the value written. you can calculate the value in the tcr register in interval timer mode as follows. note that the instruction cycle is the oscillator frequency divided into four cycles (4/fc). tcr register value = 2 16 - (interval time/instruction cycle) set the upper 8 bits as the tchr register and the lower 8 bits as the tclr register. note: the value that is set in this register is valid only when the counter is started for the first time. the counter, if it overflows, counts up from 0000 h . a value must be written in this register while the counter is stopped (tmcr: tcs=0). a value can be read from this register even while the counter is operating. always use a word transfer instruction (such as movw a, 0019h) to read this register. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 4 h address 00000000 b initial value r rr rr r r r r/w r/w r/w r/w r/w r/w r/w upper byte (tchr) r/w r rr rr r r r 00000000 b 0 0 7 5 h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lower byte (tclr) address initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled r : read only --> while the counter is stopped --> while the counter is operating --> while the counter is stopped --> while the counter is operating
243 9.5 16-bit timer/counter interrupts 9.5 16-bit timer/counter interrupts a 16-bit timer/counter interrupt is caused by: ? an overflow in interval timer function mode (ffff h --> 0000 h ) ? an overflow in the 16-bit counter function mode (ffff h --> 0000 h ) n interrupts in interval timer function mode if the counter counts up from the defined counter value according to the internal count clock until it overflows, the interrupt request flag bit (tmcr: tcef) is set to 1. if, at this time, the interrupt request enable bit is set to enabled (tmcr: tcie=1), an interrupt request (irqd) occurs in the cpu. use the interrupt processing routine to write 0 to the tcef bit and clear the interrupt request. if the counter is cleared (tmcr: tcr=0) and the counter value overflows at the same time, the tcef bit is not set. while the tcef bit is 1, setting the tcie bit from disabled to enabled (0 to 1) immediately causes an interrupt request. the tcef bit is set whenever the counter value overflows regardless of the value in the tcie bit. n interrupts in counter function mode if the counter counts up from the defined counter value each time preset edge is detected until it overflows, the interrupt request flag bit (tmcr: tcef) is set to 1. if, at this time, the interrupt request enable bit is set to enabled (tmcr: tcie=1), an interrupt request (irqd) occurs in the cpu. use the interrupt processing routine to write 0 to the tcef bit and clear the interrupt request. if the counter is cleared (tmcr: tcr=0) and the counter value overflows at the same time, the tcef bit is not set. while the tcef bit is 1, setting the tcie bit from disabled to enabled (0 to 1) immediately causes an interrupt request. the tcef bit is set whenever the counter value overflows regardless of the value in the tcie bit. n register related to the interrupts of the 16-bit timer/counter and the vector table for the operation of interrupts, see section 3.4.2 "interrupt processing". table 9.5-1 register related to the interrupts of the 16-bit timer/counter and the vector table interrupt name interrupt level setting register vector table address register bit to be set upper lower irqd ilr4 (007e h ) ld1 (bit 3) ld0 (bit 2) ffe0 h ffe1 h
244 chapter 9 16-bit timer/counter 9.6 operation of the interval timer function this section describes the operation of the interval timer function of the 16-bit timer/ counter. n operation of the interval timer function for interval timer function operation, the setting shown in figure 9.6-1 "setting the interval timer function" is necessary. figure 9.6-1 setting the interval timer function if the counter is started (tmcr: tcs=1), the counter starts counting up from the value in the tcr register on every rising edge of the internal count clock (1 t inst : the oscillator frequency divided into four cycles). if the counter overflows (ffff h --> 0000 h ), the interrupt request flag bit is set (tmcr: tcef=1). after an overflow, the counter starts counting up from 0000 h . figure 9.6-2 "operation of the interval timer" shows the operation of the interval timer. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmcr : used 1 : set to 1 0 : set to 0 tcs tcie tcef tcs0 tcs1 tcr tchr tclr set to the initial value of the counter (upper 8 bits) set to the initial value of the counter (lower 8 bits)
245 9.6 operation of the interval timer function figure 9.6-2 operation of the interval timer note: do not write a value to the tcr register while the interval timer function is operating (tmcr: tcs=1) timer cycle time timer cycle ffff h counter value 0080 h 0000 h tcr value (0000 h ) tcef bit tcs bit stop start restart cleared by the program *1: the timer operation is stopped and the tcr value changes (0000 h --> 0080 h ). timer operation then starts again. *2: the counter, when an overflow occurs, starts counting from 0000 h . the program clears the counter (tmcr: tcr=0) changing the tcr value *1(0080 h ) overflow *2 stop
246 chapter 9 16-bit timer/counter 9.7 operation of the counter function this section describes the operation of the counter function of the 16-bit timer/ counter. n operation of the counter function to the counter function operation, the setting shown in figure 9.7-1 "setting the counter function", "setting the counter function," is necessary figure 9.7-1 setting the counter function if the counter is started (tmcr: tcs=1), the counter starts counting up from the value in the tcr register whenever the prespecified edge of a pulse that is input to the ec pin (the external count clock) is detected. if the counter overflows (ffff h --> 0000 h ), the interrupt request flag bit is set (tmcr: tcef=1). then, if the next prespecified edge is input, the counter starts counting up from 0000 h .figure 9.7-2 "16-bit counter operation" shows the operation when the counter operation mode select bits (tmcr: tcs1, tcs0) are set to 11 b (detecting both edges) and the tcr register to 0000 h . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmcr 1 other than 00 : used x : not used 1 : set to 1 0 : set to 0 tcs tcie tcef tcs0 tcs1 tcr - - tchr tclr set to the initial value of the counter (upper 8 bits) set to the initial value of the counter (lower 8 bits) ddr8
247 9.7 operation of the counter function figure 9.7-2 16-bit counter operation note: do not write a value to the tcr register while the counter function is operating (tmcr: tcs=1) external input pulse (ec pin input waveform) counter value ffff h 0000 h tcef bit tcs bit cleared by the program
248 chapter 9 16-bit timer/counter 9.8 status of the 16-bit timer/counter in each mode this section describes the operations of switching to the sleep and stop modes and of receiving a suspend request while the 16-bit timer/counter is operating. n operation in low power consumption (standby) mode and when the counter is suspended figure 9.8-1 "operation of the counter in low power consumption (standby) mode and when the counter is suspended" shows the status of the counter value upon switching to the sleep and stop modes and upon receiving a suspend request while the interval timer or counter function is operating. in stop mode, the counter stops, retaining the value. if stop mode is cleared by an external interrupt, the counter starts counting from the retained value. therefore, the initial interval time and the input pulse edge count cannot be correct values. after stop mode is cleared, initialize the 16-bit timer/counter again. figure 9.8-1 operation of the counter in low power consumption (standby) mode and when the counter is suspended the counter value is retained while the counter is stopped (tmcr: tcs=0). timer cycle time counter value ffff h tcr value (0000 h ) tcef bit tcs bit start sleep slp bit (stbc register) stp bit (stbc register) stop cleared by an external interrupt 0000 h cleared by the program restart stop stop suspend stop request oscillation stabilization wait time sleep cleared by irqf
249 9.9 notes on using the 16-bit timer/counter 9.9 notes on using the 16-bit timer/counter this section contains notes on using the 16-bit timer/counter. n notes on using the 16-bit timer/counter m error in interval timer function mode, starting of the counter by the program and starting of count-up by the internal count clock are asynchronous. thus, an error of one less instruction cycle at the most may exist in the time elapsing until the counter overflows. figure 9.9-1 "error until the count operation is started" shows an error until the count operation is started. figure 9.9-1 error until the count operation is started m notes on setting the program ? write a value to the tcr register while the counter operation is stopped (tmcr: tcs=0). a value can be read even while the counter is counting. however, always use a word transfer instruction (such as movw a, dir) to read this register. ? change the counter operation mode select bits (tmcr: tcs1, tcs0) while the counter is stopped (tmcr: tcs=0), an interrupt is disabled (tcie=0), and the interrupt request is cleared (tcef=0). ? if the interrupt request flag bit (tmcr: tcef) is 1 and the interrupt request is enabled (tmcr: tcie=1), the counter cannot restored after interrupt processing. always clear the tcef bit. ? if the counter is cleared (tmcr: tcr=0) and the counter value overflows at the same time, the interrupt request flag bit (tmcr: tcef) is not set. timer count register (tcr) value count clock n+2 n+3 setting value: n n+1 n+4 counter started one cycle error setting value: n cycles
250 chapter 9 16-bit timer/counter 9.10 programe example of the 16-bit timer/counter this section contains sample programs for the 16-bit timer/counter. n program example of the interval timer function m processing specification ? generate a 20-ms interval timer interrupt. ? use the interrupt processing routine to reset the tcr register and generate an interrupt repeatedly. ? the following shows the tcr register value for an interval time of 20 ms when the oscillator frequency is 10 mhz. ? tcr register value = 2 16 - 20 ms / (4/10 mhz) = 15536 (3cb0h) m coding example tmcr .equ 0073h ; address of the timer control reister tchr .equ 0074h ; upper address of the timer count register tclr .equ 0075h ; lower address of the timer count register tcef .equ tmcr:2 ; definition of the interrupt request flag bit tcs .equ tmcr:0 ; definition of the count start bit ilr4 .equ 007eh ; address of the interrupt level setting register .section int_v, data, locate=0 ; [data segment] .org 0ffdch irqd .data.h wari ; setting interrupt vector ;int_v ends ;----main program--------------------------------------------------- ----- .section cseg, code, align=1 ; [code segment] ; stack pointer (sp) and other are assumed to have been initialized : clri ; interrupt disable clrb tcs ; count operation stop mov ilr4,#11110111b ; setting interrupt level (level 1) mov tchr,#03ch ; set the 20 ms timer data mov tclr,#0b0h mov tmcr,#00100011b ; retain the counter value, set the interval timer operation, clearing the interrupt request flag, enabling interrupt request output, and start counter operation seti ; interrupt enable : ;----interrupt program------------------------------------------------ wari
251 9.10 programe example of the 16-bit timer/counter mov tmcr,#00100000b ; clearing interrupt request flag and stop counter operatin pushw a xchw a,t pushw a movw a,tchr ; add the time from the overflow to the interrupt acceptance mov a,#3cb0h ; 20 ms timer data (at 10 mhz) clrc addcw a ; here, an overflow during addition is not considered movw tchr,a ; strictly, the time while the counter is stopped must be added mov tmcr,#00100011b ; enable the interrupt, and start counting : user processing : popw a xchw a, t popw a reti ends ;------------------------------------------------------------------- .end
252 chapter 9 16-bit timer/counter n program example of the counter function m processing specifications ? generate an interrupt whenever the rising edge of a pulse being input to the ec pin is counted 10,000 times. ? use the interrupt processing routine to reset the tcr register and generate an interrupt repeatedly. ? the following shows the tcr register value at which the counter overflows when a rising edge is detected 10,000 times. ? tcr register value = 2 16 - 10000 = 65536 - 10000 = 55536 = d8f0h m coding example tmcr .equ 0073h ; address of the timer control reister tchr .equ 0074h ; upper address of the timer count register tclr .equ 0075h ; lower address of the timer count register tcef .equ tmcr:2 ; definition of the interrupt request flag bit tcs .equ tmcr:0 ; definition of the count start bit ilr4 .equ 007eh ; address of the interrupt level setting register .section int_v, data, locate=0 ; [data segment] .org 0ffdch irqf .data.h wari ; setting interrupt vector ;int_v ends ;----main program--------------------------------------------------- ----- .section cseg, code, align=1 ; [code segment] ; stack pointer (sp) and other are assumed to have been initialized : clri ; interrupt disable clrb tcs ; count operation stop mov ilr4,#01111111b ; setting interrupt level (level 1) mov tchr,#0d8h ; initialize the counter value mov tclr,#0f0h mov tmcr,#00110011b ; retain the counter value, set the counter function (selecting the rising edge of external input), clearing the interrupt request flag, enabling the interrupt request output, and enabling the counter operation seti ; interrupt enable : ;----interrupt program------------------------------------------------ wari clrb tcef ; clearing interrupt request flag pushw a xchw a,t pushw a clrb tcs ; stop counter operation
253 9.10 programe example of the 16-bit timer/counter mov a,0d8h ; initialize the counter value mov tchr,a ; here, the pulse after overflow is ignored mov a,#0f0h mov tclr,a setb tcs ; restart the count operation, and start counting 10,000 pulses from here : user processing : popw a xchw a, t popw a reti ends ;------------------------------------------------------------------- .end
254 chapter 9 16-bit timer/counter
255 chapter 10 external interrupts (edges) this chapter describes the functions and operations of the external interrupt circuit (edge). 10.1 "overview of the external interrupt circuit" 10.2 "configuration of the external interrupt circuit" 10.3 "pins of the external interrupt circuit" 10.4 "registers of the external interrupt circuit" 10.5 "external interrupt circuit interrupts" 10.6 "operation of the external interrupt circuit"
256 chapter 10 external interrupts (edges) 10.1 overview of the external interrupt circuit the external interrupt circuit detects edges of the signal input into the four external interrupt pins to issue an interrupt request to cpu. n external interrupt function the external interrupt circuit has a function to detect edges of the signal input into the external interrupt pins to issue an interrupt request to cpu, which makes a return from the standby mode and a transition to a normal operation state (main run state) possible. ? external interrupt pin: four (p80/int0 to p83/int3) ? external interrupt source: signal input of any edge to the external interrupt pins ? interrupt control: permission and prohibition of the interrupt request output by the interrupt request enable bit of the external interrupt control registers (eic1 to eic2) ? interrupt flag: detection of the specified edges by the external interrupt request flag bit of the external interrupt control registers (eic1 to eic2) ? interrupt request: issued according to each external interrupt source (irq0, irq1)
257 10.2 configuration of the external interrupt circuit 10.2 configuration of the external interrupt circuit the external interrupt circuit comprises the following two elements: ? edge detection circuit (0 to 3) ? external interrupt control register (eic1 to 2) n block diagram of the external interrupt circuit figure 10.2-1 block diagram of the external interrupt circuit m edge detection function if the edge polarity of the signal input into the external interrupt pins (int0 to int3) and that (sl01 to sl31, sl00 to sl30) selected by the eic1 to eic2 registers match, the corresponding external interrupt request flag bit (eir0 to eir3) is set to "1". m external interrupt control register (eic1 to eic2) the eic1 to eic2 registers are used to select the edges, allow/prohibit interrupt requests, and check interrupt requests. m interrupt sources of external interrupts irq0: if the interrupt request output is allowed (eic1: eie0=1, eie1=1), an interrupt request is issued when an edge of the selected polarity enters the external interrupt pin int0 or int1. irq1: if the interrupt request output is allowed (eic2: eie2=1, eie3=1), an interrupt request is issued when an edge of the selected polarity enters the external interrupt pin int2 or int3. eir1 1 0 p81/int1 1 0 external interrupt control register eic1 (eic2) sl10 eie1 eir0 sl00 eie0 edge detection circuit 1 (3) edge detection circuit 0 (2) selector selector pin pin irq0 (irq1) sl11 sl01 p80/int0 (p82/int2) (p83/int3)
258 chapter 10 external interrupts (edges) 10.3 pins of the external interrupt circuit this section describes the pins related to the external interrupt circuit and provides a block diagram of the pins. n pins related to the external interrupt circuit the pins related to the external interrupt circuit are the p80/int0 to p83/int3 pins. m p80/int0 to p83/int3 pins these pins provide the function as a general-purpose i/o dedicated port (p80 to p83) and also serve for external interrupt input (hysteresis input) (int0 to int3). if the interrupt request output is not allowed, an interrupt request is not output. the pin state can be read directly through the port data register (pdr8). table 10.3-1 "pins related to the external interrupt circuit" lists the pins related to the external interrupt circuit. table 10.3-1 pins related to the external interrupt circuit external interrupt pin used for external interrupt input (interrupt request output allowed) used as an input dedicated port (interrupt request output prohibited) p80/int0 int0 (eic1:eie0=1) p80 (eic1:eie0=0) p81/int1 int1 (eic1:eie1=1) p81 (eic1:eie1=0) p82/int2 int2 (eic2:eie2=1) p82 (eic2:eie2=0) p83/int3 int3 (eic2:eie3=1) p83 (eic2:eie3=0) int0 to int3: if an edge of the selected polarity enters these pins, an interrupt corresponding to the pin is generated.
259 10.3 pins of the external interrupt circuit n block diagram of the pins related to the external interrupt circuit figure 10.3-1 block diagram of the pins related to the external interrupt circuit note: at the stop mode (spl=1), the external interrupt input becomes input enable state and cutting off the external interrupt input buffer, even if the edge polarity selection bit was selected to the rising edge, falling edge, or both edges. in that case, it should be fix the voltage level by using the external pull-up resistor or pull-down resistor. p-ch n-ch ddr p80/int0 p83/int3 edge selection bit to external interrupt circuit pin pdr read pdr read (for bit manipulation instructions) pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode spl: pin state designate bit of the standby control register (stbc) ddr (port direction register)
260 chapter 10 external interrupts (edges) 10.4 registers of the external interrupt circuit this section describes the registers related to the external interrupt circuit. n registers related to the external interrupt circuit figure 10.4-1 registers related to the external interrupt circuit eir1 sl10 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 a h address 00000000 b initial value r/w sl01 eie0 r/w r/w r/w r/w eie1 eir0 r/w int1 int0 r/w : read/write enabled x : undefined eic1 (external interrupt control register 1) sl00 sl11 r/w r/w eir3 sl30 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 b h address 00000000 b initial value r/w sl21 eie2 r/w r/w r/w r/w eie3 eir2 r/w int3 int2 eic2 (external interrupt control register 2) sl20 sl31 r/w r/w
261 10.4 registers of the external interrupt circuit 10.4.1 external interrupt control register (eic1 to eic2) the external interrupt control registers (eic1 to eic2) are used to select the edge polarity for the external interrupt pins int0 to int3 and control interrupts. this section shows the register configuration using eic1 as an example. n external interrupt control register (eic1) figure 10.4-2 external interrupt control register (eic1) external interrupt request flag bit 0 r/w eir1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 a h address 00000000 b initial value sl00 eie0 r/w sl10 r/w r/w r/w eie1 eir0 r/w eir0 0 1 sl01 0 0 1 1 eie0 0 1 specified edge is not entered specified edge is entered read clear this bit no change and does not affect others write no edge detection rising edge falling edge both rising and falling edges prohibit interrupt request output allow interrupt request output int0 (irq0) r/w : read/write enabled x : undefined : initial value interrupt request enable bit 0 edge polarity selection bit 0 external interrupt request flag bit 0 no specified edge entered specified edge entered clear this bit no change and does not affect others no edge detection rising edge falling edge both rising and falling edges prohibit interrupt request output allow interrupt request output interrupt request enable bit 0 edge polarity selection bit 0 sl01 sl11 r/w r/w sl00 0 1 0 1 int1 (irq0) eir1 0 1 sl11 0 0 1 1 eie1 0 1 read write sl10 0 1 0 1
262 chapter 10 external interrupts (edges) table 10.4-1 explanation of functions of each bit of the external interrupt control register (eic1) bit name function bit 7 eir1: external interrupt request flag bit 1 ? "1" is set if the edge selected by the edge polarity selection bit 1 (sl11, sl10) is entered in the external interrupt pin int1. ? if this bit and the interrupt request enable bit 1 (eie1) are "1", an interrupt request is output. ? this bit is cleared by writing "0". if "1" is written, this bit is not affected and changed. bit 6 bit 5 sl11, sl10: edge polarity selection bit 1 ? bits to select the polarity of edges to be an interrupt source for pulses input into the external interrupt pin int1. bit 4 eie1: interrupt request enable bit 1 ? bit to allow/prohibit interrupt request output to cpu. if this bit and the external interrupt request flag bit 1 (eir1) are "1", an interrupt request is output. bit 3 eir0: external interrupt request flag bit 0 ? "1" is set if the edge selected by the edge polarity selection bit 0 (sl01, sl00) is entered in the external interrupt pin int0. ? if this bit and the interrupt request enable bit 0 (eie0) are "1", an interrupt request is output. ? this bit is cleared by writing "0". if "1" is written, this bit is not affected and changed. bit 2 bit 1 sl01, sl00: edge polarity selection bit 0 ? bits to select the polarity of edges to be an interrupt source for pulses input into the external interrupt pin int0. bit 0 eie0: interrupt request enable bit 0 ? bit to allow/prohibit interrupt request output to cpu. if this bit and the external interrupt request flag bit 0 (eir0) are "1", an interrupt request is output.
263 10.5 external interrupt circuit interrupts 10.5 external interrupt circuit interrupts as an interrupt source of the external interrupt circuit, the detection of the specified edge of a signal input into the external interrupt pin is available. n interrupts when the external interrupt circuit is operating if the specified edge of the external interrupt input is detected, "1" is set to the corresponding external interrupt request flag bit (eic1: eir0 to eir1/eic2: eir2 to eir3). at this time, if the corresponding interrupt request enable bit is set (eic1: eie0 to eie1=1/eic2: eie2 to eie3=1), an interrupt request (irq0, irq1) to cpu is issued. the following table lists the correspondence of the interrupt requests (irq0 to irq1). if no external interrupt is used to return from the stop mode, set "00" to the edge polarity bits and "0" to the interrupt enable bit. note: to allow interrupts (eie0 to eie2=1) after releasing a reset, clear (eir0 to eir2=0) the external interrupt request flag bit at the same time. it is not possible to return from interrupt processing if the external interrupt request flag bit is "1" and the interrupt request enable bit is set. the external interrupt request flag bit in interrupt processing routines must be cleared. the release of the stop mode by an interrupt is possible only in the external interrupt circuit. if the interrupt request enable bit is changed from prohibition to permission (0 --> 1), an interrupt occurs immediately. n register and vector table related to interrupts of the external interrupt circuit for interrupt operations, see section 3.4.2 "interrupt processing". interrupt request (int) interrupt request to cpu int0 irq0 int1 int2 irq1 int3 table 10.5-1 register and vector table related to interrupts of the external interrupt circuit interrupt name interrupt level setting register vector table address register bit to be set upper lower irq0 ilr1 (007b h ) l01 (bit 1) l00 (bit 0) fffa h fffb h irq1 ilr1 (007b h ) l11 (bit 3) l10 (bit 2) fff8 h fff9 h
264 chapter 10 external interrupts (edges) 10.6 operation of the external interrupt circuit the external interrupt circuit can detect the specified edge of signal input into the external interrupt pins. this section describes the operations, using int0 as an example. n operations of the external interrupt circuit the setting in figure 10.6-1 "setting of the external interrupt circuit" is required for the operation of int0 of the external interrupt circuit. figure 10.6-1 setting of the external interrupt circuit if the edge polarity of the signal input from the external interrupt pin (int0) and that (eic1: sl01, sl00) selected by the external interrupt control register match, the corresponding external interrupt request flag bit (eic1: eir0) is set to "1". the external interrupt request flag bit is set if the polarity of edges match, regardless of the interrupt request enable bit (eic1: eie0). figure 10.6-2 "operations of the external interrupts (int0)" shows the operations when the int0 pin is used for external interrupt input. figure 10.6-2 operations of the external interrupts (int0) if the pins are used for external interrupt input, the pin states can be read directly from the port data register (pdr8) provided the analog input is not allowed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 : bit used eic1 eir1 eie0 sl00 eir0 eie1 sl10 sl01 sl11 input waveform into int0 pin sl01 bit eie0 bit eir0 bit clear the interrupt request flag bit by programs clear simultaneously with the eie0 bit setting sl00 bit rising setting falling setting irq0
265 chapter 11 a/d converter this chapter describes the functions and operations of the a/d converter. 11.1 "overview of the a/d converter" 11.2 "configuration of the a/d converter" 11.3 "pins of the a/d converter" 11.4 "registers of the a/d converter" 11.5 "a/d converter interrupt" 11.6 "operation of the a/d converter" 11.7 "notes on using the a/d converter" 11.8 "program example of the a/d converter"
266 chapter 11 a/d converter 11.1 overview of the a/d converter the a/d converter is a 10-bit successive approximation type that selects one input signal from 12-channel analog pins. it can be started by software. n a/d conversion function the a/d conversion function converts an analog voltage entering at an analog input pin (input voltage) to a 10-bit digital value. ? one signal can be selected from 12 analog input pins. ? the conversion rate is 60 instruction cycles (24 m s at 10 mhz main clock oscillation). ? an interrupt occurs when a/d conversion is complete. ? the end of conversion can also be checked with software. the a/d conversion function can be started by software.
267 11.2 configuration of the a/d converter 11.2 configuration of the a/d converter the a/d converter consists of the following nine blocks: ? analog channel selector ? sample hold circuit ? d/a converter ? comparator ? control circuit ? a/d data registers (addh, addl) ? a/d control registers 1, 2 (adc1, 2) n block diagram of the a/d converter figure 11.2-1 a/d converter block diagram m analog channel selector the analog channel selector circuit selects one signal from 12 analog input pins. internal data bus a/d data registers (addh, addl) control circuit d/a converter analog channel selector avr avss p10/an4 p11/an5 p12/an6 p13/an7 p14/an8 p15/an9 p16/an10 p17/an11 comparator irq3 sample hold circuit resv adck adie admd ext resv a/d control register 2 (adc2) adi admv sifm ad a/d control register 1 (adc1) avcc resv f ch : main clock oscillation ans3 ans2 ans1 ans0 p85/an0 p86/an1 p87/an2 p90/an3
268 chapter 11 a/d converter m sample hold circuit the sample hold circuit holds the input voltage selected by the analog channel selector. by sampling and holding the input voltage immediately after a/d conversion, the analog voltage can be digitized without being affected by input voltage fluctuations during a/d conversion (comparison). m d/a converter generates a voltage corresponding to the value set in the addh and addl registers. m comparator compares the sampled and held input voltage with the voltage output from the d/a converter and indicates whether the d/a output is greater or less than the input voltage. m control circuit the control circuit has the following function: ? in the a/d conversion function, sets the bits in the 10-bit a/d data register from the most significant bit to the least significant bit according the signals from the comparator indicating whether the d/a output is greater or less than the input voltage. the control circuit sets the interrupt request flag bit (adc1: adi) when the conversion is complete. m a/d data registers (addh/addl) the upper two bits of the 10-bit a/d data are stored in the addh register, and the lower eight bits are stored in the addl register. the result of a/d conversion is stored in the addh/addl registers. m a/d control register 1 (adc1) enables and disables the functions of the a/d converter, selects an analog input pin, checks the state, and controls interrupt. m a/d control register 2 (adc2) enables and disables interrupts. m ad converter interrupts irq3: when a/d conversion is complete, an interrupt request is issued if interrupt request output is enabled (adc2: adie = 1). n a/d converter power supply voltage m avcc power supply pin for the a/d converter. use the same potential that is used for vcc. if extreme a/d conversion accuracy is required, make sure that avcc is free of vcc noise or use another power supply. if the a/d converter is not used, still connect this pin to the power supply. m avss ground pin for the a/d converter. use same potential as that is used for vss. if extreme a/d conversion accuracy is required, make sure that avss is free of vss noise or use another power supply. if the a/d converter is not used, still connect this pin to ground (gnd).
269 11.2 configuration of the a/d converter m avr pin to inputting the reference voltage for the a/d converter. 10-bit a/d conversion is performed between avr and avss. if the a/d converter is not used, connect it to avss.
270 chapter 11 a/d converter 11.3 pins of the a/d converter this section describes the pins related to the a/d converter and shows a block diagram. n pins related to a/d converter the pins related to the a/d converter are p85/an0 to p87/an2, p90/an3, and p10/an4 to p17/ an11. m p85/an0/sw1 to p87/an2/sw3 pins p85/an0/sw1 to p87/an2/sw3 function as a general-purpose output port (p85 to p87), as analog input pins (an0 to an2), and as a comparator (sw1 to sw3). m p90/an3 pin p90/an3 functions as a general-purpose i/o port (p90) and as an analog input pin (an3). m p10/an4 to p17/an11 pins p10/an4 to p17/an11 function as a general-purpose i/o port (p10 to p17) and as analog input pin (an5 to an11). an0 to an11 to use the a/d conversion function, input the analog voltage to be converted to these pins. when the corresponding bits in the port data registers (ddr8, ddr9, ddr1) are set to 0, the output transistor is turned off, and a pin is selected with the analog input channel select bits (adc2: ans0 to ans3), the selected pin functions as an analog input pin. the pins that are not used as analog input pins can be used as a general-purpose i/o port.
271 11.3 pins of the a/d converter n block diagram of pins related to the a/d converter figure 11.3-1 block diagram of pins p85/an0 to p87/an2 pin p-ch n-ch pdr read pdr write ddr write output latch stop/watch mode(spl=1) pdr (port data register) ddr internal data bus (port direction register) stop/watch mode ddr (port direction register) a/d input enable bit a/d converter channel selection bit to a/d converter analog input comparator control bit p85/an0/swi1 p87/an2/sw3 comparator operation enable bit comparator spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
272 chapter 11 a/d converter figure 11.3-2 block diagram of pin p90/an3 figure 11.3-3 block diagram of pins p10/an4 to p17/an11 p-ch n-ch ddr p90/an3 internal data bus pdr (port data register) pdr read output latch pdr write (port direction register) ddr write ddr (port direction register) stop/watch mode(spl=1) to a/d converter analog input stop/watch mode pin a/d converter channel selection bit a/d input enable bit spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions) p-ch n-ch ddr p10/an4 p17/an11 pin pdr read pdr write ddr write output latch stop/watch mode(spl=1) pdr (port data register) internal data bus (port direction register) stop/watch mode ddr (port direction register) a/d input enable bit a/d converter channel selection bit to a/d converter analog input spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
273 11.4 registers of the a/d converter 11.4 registers of the a/d converter this section shows the registers related to the a/d converter. n registers related to a/d converter figure 11.4-1 registers related to the a/d converter ans0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 2 f h address 000000x0 b initial value adi - ad admv r r/w r/w r/w adck bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 0 h address x0000001 b initial value adie ext resv admd r/w r/w r/w r/w r/w r/w resv resv r/w adc1 (a/d control register 1) adc2 (a/d control register 2) ans1 ans2 ans3 - r/w r/w r/w r/w r/w r/w r/w r/w r/w d9 d8 d1 d0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 2 h address xxxxxxxx b initial value r/w r/w r/w r/w d7 d6 d5 d4 d3 d2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 3 h address xxxxxxxx b initial value addh, addl (a/d data register) - - -- - - bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 2 d h address xxxx1111 b initial value ade0 ade2 r/w r/w r/w r/w aden1 (a/d enable register 1) ade3 ade1 ade8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 2 e h address 11111111 b initial value ade4 ade6 r/w r/w r/w r/w r/w r/w ade10 ade9 r/w aden2 (a/d enable register 2) ade7 ade5 ade11 r/w - - - - r/w r x : read/write enabled : read only : undefined
274 chapter 11 a/d converter 11.4.1 a/d control register 1 (adc1) the a/d control register 1 (adc 1) enables and disables the functions of the a/d converter and checks the state. n a/d control register 1 (adc1) figure 11.4-2 a/d control register 1 (adc1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 2 f h address 000000x0 b initial value adi 0 1 interrupt request flag bit during a read during a write conversion has not been completed. conversion is complete. the bit is cleared. there is no change, and there is no effect on other bits. admv 0 1 conversion is not in progress. conversion is in progress. ad 0 1 software start time a/d conversion function has not started. a/d conversion function has started. adi - ad r r/w r/w a/d conversion start bit conversion flag bit ans0 ans1 ans2 ans3 ans3 0 0 0 0 0 0 0 0 1 1 1 1 ans2 0 0 0 0 1 1 1 1 0 0 0 0 ans1 0 0 1 1 0 0 1 1 0 0 1 1 ans0 0 1 0 1 0 1 0 1 0 1 0 1 analog input channel select bit an0 pin an1 pin an2 pin an3 pin an4 pin an5 pin an6 pin an7 pin an8 pin an9 pin an10 pin an11 pin admv r/w r/w r/w r/w r/w r - x : read/write enabled : read only : unused : undefined : initial value
275 11.4 registers of the a/d converter table 11.4-1 functions of the a/d control register 1 (adc1) bits bit name function bit 7 bit 6 bit 5 bit 4 ans3, ans2, ans1, ans0: analog input channel select bits ? these bits select a pin to be used as an analog input pin from an0 to an11. ? these bits can be rewritten when the a/d conversion function is started (ad = 1). note: do not rewrite these bits when the adc1:admv bit is 1. reference: the pins that are not used as analog input pins can be used as general-purpose ports. bit 3 adi: interrupt request flag bit ? in a/d conversion function operation, this bit is set to 1 when a/d conversion is completed. ? for a write operation, writing 0 clears this bit. writing 1 has no effect and no effects on other bits. bit 2 admv: conversion flag bit ? in the a/d conversion function operation, this bit indicates that conversion is being performed. ? during conversion, this bit is set to 1. reference: this bit is read only. writing to this bit has no meaning and has no effect on operation. bit 1 unused bit ? the read value is undefined. ? writing has no effect on operation. bit 0 ad: a/d conversion start bit ? this bit starts the a/d conversion function from software. ? writing 1 to this bit starts the a/d conversion function. note: ? even though 0 is written to this bit, the operation of the a/ d conversion function cannot be stopped. the read value is always 0.
276 chapter 11 a/d converter 11.4.2 a/d control register 2 (adc2) the a/d control register 2 (adc 2) selects the functions of the a/d converter, selects the input clock, enables and disables interrupts and continuous start, and checks the state. n a/d control register 2 (adc2) figure 11.4-3 a/d control register 2 (adc2) r/w r/w r/w r/w r/w r/w adck bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 0 h address x0000001 b initial value resv - resv adie admd ext resv r/w adie 0 1 disables interrupt request output. enables interrupt request output. admd function selection bit ext be sure to write 0 to this bit. resv resv reserved bit be sure to write 1 to this bit. reserved bit be sure to write 0 to this bit. interrupt request enable bit reserved bit adck be sure to write 0 to this bit. reserved bit be sure to write 0 to this bit. r/w - x : read/write enabled : unused : undefined : initial value
277 11.4 registers of the a/d converter table 11.4-2 functions the a/d control register 2 (adc2) bits bit name function bit 7 unused bit ? the read value is undefined. ? writing has no effect on operation. bit 6 bit 5 resv: reserved bit ? be sure to write 0 to this bit. bit 4 adck: reserved bit ? be sure to write 0 to this bit. bit 3 adie: interrupt request enable bit ? this bit enables and disables interrupt output to the cpu. ? when this bit and the interrupt request flag bit (adc1: adi) are 1, an interrupt request is output. bit 2 admd: reserved bit ? be sure to write 0 to this bit. bit 1 ext: reserved bit ? be sure to write 0 to this bit. bit 0 resv: reserved bit note: ? be sure to write 1 to this bit. ? the read value is always 1.
278 chapter 11 a/d converter 11.4.3 a/d data registers (addh, addl) these data registers store the result of a/d conversion. the upper two bits of the 10-bit data correspond to the addh register, and the lower eight bits correspond to the addl register. n a/d data registers (addh, addl) figure 11.4-4 "a/d data registers (addh, addl" shows the bit configuration of the a/d data register. figure 11.4-4 a/d data registers (addh, addl) the upper two bits of the 10-bit a/d data correspond to bits 1 and 0 of the addh register, and the lower eight bits correspond to bits 7 to 0 of the addl register. m a/d conversion cycle when a/d conversion is started, the conversion result data is determined after about 60 instruction cycles and is stored in these registers. between the completion of a/d conversion and the start of the next a/d conversion cycle, read the contents of these registers (conversion result), write 0 to adi (bit 3) of the adc1 register, and clear the flag when conversion is complete. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 2 h address xxxxxxxx b initial value r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 3 h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w d5 d7 d8 d0 d1 d6 d9 - - - - - - d2 d3 d4 r/w - x : read/write enabled : unused : undefined
279 11.4 registers of the a/d converter 11.4.4 a/d enable registers 1 to 2 (aden 1 to 2) these registers specify the port used for performing a/d conversion. n a/d enable registers 1 to 2 (aden1 to 2) figure 11.4-5 "a/d enable registers 1 to 2 (aden 1 to 2)" shows the bit configuration of the a/ d enable registers. figure 11.4-5 a/d enable registers 1 to 2 (aden 1 to 2) - -- bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 2 d h address xxxx1111 b initial value - ade2 r/w r/w r/w ade3 ade1 ade0 r/w ade11 ade9 ade8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 2 e h address 11111111 b initial value r/w ade10 ade6 r/w r/w r/w r/w r/w r/w ade7 ade5 ade4 r/w ade3 to ade0 0 1 disables a/d input (port input allowed) enables a/d input (port input not allowed) a/d input enable ade11 to ade4 0 1 a/d input enable disables a/d input (port input allowed) enables a/d input (port input not allowed) aden1 aden2 r/w - x : read/write enabled : unused : undefined : initial value
280 chapter 11 a/d converter the a/d input ports are also used as general-purpose i/o ports. for the ports used for analog input, enter a 0 for the corresponding bits in the aden register. this setting prevents the dc path from being made on the a/d input port when a middle level voltage is applied to the a/d input port. table 11.4-3 functions of the a/d enable register 1 (aden1) bits bit name function bit 7 bit 6 bit 5 bit 4 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 3 ade3: an3 enable bit ? selects p90 for analog input (an3). bit 2 ade2: an2 enable bit ? selects p87 for analog input (an2). bit 1 ade1: an1 enable bit ? selects p86 for analog input (an1). bit 0 ade0: an0 enable bit ? selects p85 for analog input (an0). table 11.4-4 functions of the a/d enable register 2 (aden2) bits bit name function bit 7 ade11: an11 enable bit ? selects p17 for analog input (an11). bit 6 ade10: an10 enable bit ? selects p16 for analog input (an10). bit 5 ade9: an9 enable bit ? selects p15 for analog input (an9). bit 4 ade8: an8 enable bit ? selects p14 for analog input (an8). bit 3 ade7: an7 enable bit ? selects p13 for analog input (an7). bit 2 ade6: an6 enable bit ? selects p12 for analog input (an6). bit 1 ade5: an5 enable bit ? selects p11 for analog input (an5). bit 0 ade4: an4 enable bit ? selects p10 for analog input (an4).
281 11.5 a/d converter interrupt 11.5 a/d converter interrupt the following function is provided as the a/d converter. ? end of conversion in a/d conversion function operation n interrupt for a/d conversion function when a/d conversion is completed, the interrupt request flag bit (adc: adi) is set to 1. if the interrupt request enable bit is then set to enable (adc: adie=1), an interrupt request to the cpu (irq3) occurs. clear the interrupt request by writing 0 to the adi bit with the interrupt processing routine. the adi bit is set when a/d conversion is completed irrespective of the value of the adie bit. if the adie bit is changed from "disable" to "enable" (0 --> 1) when the adi bit is set to 1, an interrupt request occurs immediately. n register and vector table related to a/d converter interrupt for the operation of interrupts, see section 3.4.2 "interrupt processing". table 11.5-1 register and vector table related to the a/d converter interrupt interrupt name interrupt level setting register vector table address register bit to be set higher lower irq3 ilr1 (007b) l31 (bit 7) l30 (bit 6) fff4 h fff5 h
282 chapter 11 a/d converter 11.6 operation of the a/d converter the a/d converter is started by software. n starting the a/d conversion function m starting software starting of the software for the a/d conversion function requires the setting shown in figure 11.6-1 "setting the a/d conversion function (when software starts". figure 11.6-1 setting the a/d conversion function (when software starts) when a/d conversion is started, the a/d conversion function starts operation. the a/d conversion function can be restarted even during conversion. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adc2 adc1 0 0 1 0 0 0 adi - ad admv resv adck resv adie ext resv admd - ans2 ans3 ans0 ans1 addl a/d conversion value is held addh a/d conversion value is held ddr8 ddr9 0 ddr0 bit6 bit7 - - - - bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - bit2 bit1 bit0 bit5 bit4 bit3 bit2 bit1 bit0 : used : unused : set 1 : set 0 : set the bit corresponding to the pin to be used to 0. : set the bit corresponding to the pin to be used to 1. aden1 aden2 - - - - ade0 ade1 ade2 ade3 ade4 ade5 ade6 ade7 ade8 ade9 ade10 ade11
283 11.6 operation of the a/d converter n operation of a/d conversion function a/d converter operation is described in the following. the time from start to end of the a/d conversion is about 60 instruction cycles. when a/d conversion is started, the conversion flag bit is set (adc1: admv = 1) and the set analog input pin is connected to the sample hold circuit. the voltage on the analog input pin is added to the internal sample hold capacitor for about 16 instruction cycles. this voltage is held until a/d conversion is complete. the comparator compares the voltage added to the sample hold capacitor with the reference voltage for a/d conversion in order from the most significant bit (msb) to the least significant bit (lsb), and each comparison result is transferred on at a time to the addh and addl registers. after the results have been transferred, the conversion flag bit is cleared (adc1: admv = 0) and the interrupt request flag bit is set (adc1: adi = 1).
284 chapter 11 a/d converter 11.7 notes on using the a/d converter this section contains notes on using the a/d converter. n notes on using the a/d converter m input impedance of the analog input pins the a/d converter contains the sample hold circuit shown in figure 11.7-1 "equivalent circuit for analog input" and adds the voltage of the analog input pin to the sample hold capacitor in about 16 instruction cycles after a/d conversion starts. therefore, if the output impedance of the external circuit for analog input is high, the analog input voltage may not be stabilized within the analog input sampling period. to avoid this problem, keep the output impedance of the external circuit low enough to stabilize the voltage. if the output impedance of the external circuit cannot be kept low, it is recommended that an external capacitor of about 0.1 m f be added to the analog input pin. figure 11.7-1 equivalent circuit for analog input it shows the r and c values of sample and hold circuit. m notes on setting with a program ? in a/d conversion function operations, the addh and addl registers hold the previous values until a/d conversion is started. as soon as a/d conversion is started, the contents of the addh and addl registers become undefined. ? during operation of the a/d conversion function, do not reselect an analog input channel (adc1: ans3 to ans0). ? resetting, stopping, or starting the watch mode stops the a/d converter. ? if the interrupt request flag bit (adc1: adi) is set to 1 and the interrupt request is enabled (adc2: adie = 1), it is not possible to return from interrupt processing. ? be sure to clear the adi bit. comparator controller c r an0 to an11 sample & hold circuit analog channel selector close for 16 instruction cycles after activating a/d conversion table 11.7-1 r and c values of sample and hold circuit mb89p579a MB89577 mb89pv570 r: analog input equivalent resistance 7.1 k w 2.2 k w c: analog input equivalent capacitance 48.3 pf 45 pf
285 11.7 notes on using the a/d converter m note on interrupt requests when a/d conversion (adc1: ad = 1) is started and completed at the same time, the interrupt request flag bit (adc1: adi) is not set. m about errors as |avr-avss| decreases, errors become relatively larger. m order of applying a/d converter power and analog input concurrently with or before turning on power to the a/d converter and applying the analog input (an0 to an11), turn on the digital power (vcc). concurrently with or after turning off a/d converter power (avcc, avss) and disconnecting analog input (an0 to an11), turn off the digital power (vcc). when turning power to the a/d converter on and off, be careful that avcc, avss, and analog input do not exceed the voltage of the digital power. m conversion rate the conversion rate of the a/d conversion function is influenced by the clock mode and the rate switching of the main clock (gear function).
286 chapter 11 a/d converter 11.8 program example of the a/d converter this section contains a sample program for the 10-bit a/d converter. n program example of the a/d conversion function m processing specification the analog voltage input to the an4 pin is digitized by starting of the software. an interrupt is not used, and the completion of conversion is detected by the loop in the program.
287 11.8 program example of the a/d converter m coding example ddr1 .equ 0003h ; address of the port register adc1 .equ 002fh ; address of the a/d control register 1 adc2 .equ 0030h ; address of the a/d control register 2 addh .equ 0032h ; address of the a/d data register h addl .equ 0033h ; address of the a/d data register l aden .equ 002eh ; a/d port input enable register an4_pcr .equ ddr1:0 ; definition of the an5 analog input use adi .equ adc1:3 ; definition of the interrupt request flag bit admv .equ adc1:2 ; definition of the conversion flag bit ad .equ adc1:0 ; definition of the a/d conversion start bit (software start) ;----main program----------------------------------------------------- .section cseg, code, align=1 ; [code segment] : clri ; interrupt disable setb an4_pcr ; set the p10/an4 pin as an analog input pin ad_wait bbs admv,ad_wait ; a/d converter stop check loop mov adc1,#01001000b ; select analog input channel 4 (an4), clearing the interrupt request flag, and set that software starting is not used mov aden,#11111110b ; disable interrupt request output, and select the a/d conversion function. conversion time: approx. 24 m s (at 10 mhz) seti ; interrupt enable setb ad ; start the software ad_conv bbs admv,ad_conv ; a/d conversion end wait loop [approx. 24 m s (at 10 mhz)] clrb adi ; clearing the interrupt request flag move a,addh ; read the a/d conversion data (upper 2 bits) : ends ;------------------------------------------------------------------- .end
288 chapter 11 a/d converter
289 chapter 12 d/a converter this chapter describes the functions and operations of the d/a converter. 12.1 "overview of the d/a converter" 12.2 "configuration of the d/a converter" 12.3 "pins of the d/a converter" 12.4 "registers of the d/a converter" 12.5 "operation of the d/a converter"
290 chapter 12 d/a converter 12.1 overview of the d/a converter the d/a converter is an eight-bit converter that uses the r-2r method. two built-in d/ a converters for two channels are provided, and d/a control registers control the output of each independently. n d/a converter two built-in, eight-bit d/a converters for two channels are provided. the two converters can operate independently. the maximum output voltage value of the d/a converters varies depending on the reference voltage value input to the avcc pin. ? d/a converter 1: da1 ? d/a converter 2: da2
291 12.2 configuration of the d/a converter 12.2 configuration of the d/a converter figure 12.2-1 "d/a converter block diagram" shows the block diagram of the d/a converters. n block diagram of the d/a converter block figure 12.2-1 d/a converter block diagram internal data bus d/a converter data register 1 (dadr1) d/a converter data register 2 (dadr2) 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r dae1 standby control da output (p91/da1) 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r dae1 standby control da output (p92/da2) da27 da25 da24 da23 da22 da21 da20 da26 da17 da15 da14 da13 da12 da11 da10 da16 da17 da16 da15 da14 da13 da12 da11 da10 da27 da26 da25 da24 da23 da22 da21 da20
292 chapter 12 d/a converter 12.3 pins of the d/a converter this section describes the pins related to the d/a converters (da1, 2 and shows a block diagram. n pins related to the d/a converters (da1, 2) the pins related to the d/a converters include the da1, da2, av cc , and av ss pins. the av cc and av ss pins supply the analog power for the d/a converters as well as the analog power for the a/d converter. ? da1: output pin for d/a converter 1. also used as a general-purpose input-output port (p91). ? da2: output pin for d/a converter 2. also used as a general-purpose input-output port (p92). n block diagram of the pins related to the d/a converters (da1, 2) figure 12.3-1 block diagram of the pins related to the d/a converters (da1, 2) pin p-ch n-ch pdr read pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) ddr internal data bus (port direction register) stop/watch mode ddr (port direction register) from the resource output from the resource output enable bit p91/da1 p92/da2 spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
293 12.4 registers of the d/a converter 12.4 registers of the d/a converter this section describes the registers related to the d/a converter. n registers related to the d/a converter figure 12.4-1 d/a converter registers bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 1 h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w --- bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 0 h address xxxxxx00 b initial value - - dae2 dae1 - r/w r/w dacr (d/a control register) dadr1 (d/a data register 1) da17 da15 da14 da13 da11 da10 da12 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 2 h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w dadr2 (d/a data register 2) da27 da25 da24 da23 da21 da20 da22 da16 da26 r/w r/w r/w : read/write enabled x : undefined
294 chapter 12 d/a converter 12.4.1 d/a control register the d/a control register enables ands disables the output of the d/a converters 1 and 2. n d/a control register (dacr) figure 12.4-2 d/a control register (dacr) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 0 h address xxxxxx00 b initial value - - - - dae2 dae1 - r/w - dae1 0 1 d/a converter 1 (da1) output control bit output disabled output enabled dae2 0 1 d/a converter 2 (da2) output control bit output disabled output enabled r/w : read/write enabled x : undefined : initial value table 12.4-1 functions of the d/a control register (dacr) bits bit name function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 1 dae2: d/a converter 2 control bit ? controls the output of d/a converter 2 (da2) ? enables d/a output if set to 1. disables d/a output ? if set to 0. ? initialized to 0 if reset. ? can be read and written. bit 0 dae1: d/a converter 1 control bit ? controls the output of d/a converter 1 (da1) ? enables d/a output if set to 1. disables d/a output if set to 0. ? initialized to 0 if reset. ? can be read and written.
295 12.4 registers of the d/a converter 12.4.2 d/a data registers 1 and 2 (dadr1, 2) the d/a data registers set the output voltage of the d/a converters. n d/a data registers 1 and 2 (dadr1, 2) figure 12.4-3 d/a data registers 1 and 2 (dadr1, 2) dadr1 [da17 to da10]: sets the output voltage of d/a converter 1 (da1). not initialized if reset. dadr2 [da27 to da20]: sets the output voltage of d/a converter 2 (da2). not initialized if reset. r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 1 h address xxxxxxxx b initial value da17 da14 da12 da11 da10 r/w da15 r/w r/w r/w da13 r/w r/w da16 r/w dadr1 r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 7 2 h address xxxxxxxx b initial value da27 da24 da22 da21 da20 r/w da25 r/w r/w r/w da23 r/w r/w da26 r/w dadr2 r/w : read/write enabled x : undefined
296 chapter 12 d/a converter 12.5 operation of the d/a converter to start d/a output, set the d/a data register (dadr) to a desired d/a output value and set the corresponding d/a output channel enable bit in the d/a control register (dacr) to 1. n d/a converter operation disabling d/a output turns off the analog switch inserted in series into the output section of a channel of the d/a converter. it also clears the d/a converter to 0 output status and shuts off any channel where direct current runs. the same operation also occurs in stop mode. the output of this d/a converter does not contain a buffer amplifier. additionally, an analog switch is inserted in series into the output. take sufficient precautions, therefore, regarding external output load in consideration of the required settling time. the d/a converter has an output voltage range from 0 v to 255/256 x dvr. externally adjust the dvr voltage to change the output voltage range. table 12.5-1 "logical values of the d/a converter output voltage" shows the logical values of the d/a converter output voltage. table 12.5-1 logical values of the d/a converter output voltage setting value of dadr1 [da17 to da10] and dadr2 [da27 to da20] logical values of the output voltage 00h 0/256 x dvr (=0v) 01h 1/256 x dvr 02h 2/256 x dvr to to fdh 253/256 x dvr feh 254/256 x dvr ffh 255/256 x dvr
297 chapter 13 comparator this chapter describes the function and operation of the comparator. 13.1 "overview of the comparator" 13.2 "configuration of the comparator" 13.3 "pins of the comparator" 13.4 "registers of the comparator" 13.5 "comparator interrupts" 13.6 "operation of the parallel discharge control" 13.7 "operation of the sequential discharge control" 13.8 "sample application"
298 chapter 13 comparator 13.1 overview of the comparator this comparator is a circuit that monitors voltage of up to three batteries and automatically controls electric discharge. either parallel discharge or sequential discharge can be selected. n parallel discharge control in parallel discharge control, all batteries are allowed to discharge when power is not being supplied from the ac adapter. ? if power is being supplied from the ac adapter, the permission/prohibition of discharge for batteries is controlled by software. n sequential discharge control in sequential discharge control, the comparator controls discharge in a specified order, while monitoring intermittent interruption of power, voltage level, and mount/dismount of batteries, when power is not being supplied from the ac adapter. ? if power is being supplied from the ac adapter, the permission/prohibition of discharge for batteries is controlled by software. ? up to three batteries can be controlled, and the order of discharge can be selected. ? the affect of intermittent interruption of power is automatically filtered. ? mount/dismount of batteries is automatically detected and discharge is controlled. ? battery voltage is monitored, and if battery voltage is below the specified voltage, change over to the next battery is automatically done. see section 13.8 "sample application".
299 13.2 configuration of the comparator 13.2 configuration of the comparator this comparator consists of following seven blocks: ? voltage comparator ? battery monitoring circuit ? battery selection circuit ? comparator control registers 1 to 2 (cocr2) ? comparator status registers 1 to 3 (cosr1 to 3) ? comparator interrupt control registers 1 to 2 (cicr1 to 2) n comparator block diagram figure 13.2-1 comparator block diagram + - in rh rl out latch vaild alarm (2 4 /fcl) vol vsi sw pd voltage comparator reference voltage battery monitoring circuit watch prescaler ofbx output pin switching unit
300 chapter 13 comparator voltage comparator the voltage comparator uses the rh and rl pins, as reference voltage input pins for the reference voltage switching units. this implements a comparator with rh-rl hysteresis width. battery monitoring circuit the battery monitoring circuit monitors power supplied from the ac adapter and the intermittent interruption of power (vol), voltage level (vsi), and mount/dismount of batteries. when battery discharge starts, the battery monitoring circuit automatically generates an approximately 250 m s to 500 m s of delay from change of vol by the subclock. battery selection circuit the battery selection circuit controls the selection of a battery discharge method and the order of discharge, based on the values set in the cocr register 1 (cocr1:spm0, 1, 2). comparator control register 1 (cocr1) this register is used to set a sequence for the battery selection circuit and to disable battery discharge. comparator control register 2 (cocr2) this register is used to allow operation of the comparator and control output from ports. comparator status register 1 (cosr1) this register holds and stores an edge change in signals that are output from comparator 1 and voltage comparators 2 to 8. this allows confirmation of a battery voltage change. comparator interrupt control register 1 (cicr1) when an edge change is detected in an output signal by the cosr1 register, this register allows an interrupt to be generated. comparator status register 2 (cosr2) this register holds and stores output from comparators 2 to 4 and an edge change in a valid signal from the battery monitoring circuit. this allows the detection of mounting/ dismounting of batteries and the status changes of batteries. comparator interrupt control register 2 (cicr2) the cicr2 controls enabling an interrupt when the outputs from comparators 2 to 4 together with the change of edges of valid signal from the battery monitoring circuit are seized by the cosr2 register. comparator status register 3 (cosr3) this register stores a valid signal value that is output from the battery monitoring circuit . this allows a valid signal output value to be confirmed. comparator status register 4 (cosr4) this register can directly read values that are output from comparator 1 and voltage comparators 2 to 8.
301 13.2 configuration of the comparator interrupts associated with the comparator irq4: when a change is detected in a output signal that is output from comparator 1 and voltage comparators 2 to 8, an interrupt is generated if interrupt generation has been allowed (cicr1). irq5: when a change is detected in a valid signal that is output from the battery monitoring circuit or when a change is detected in the output from the comparators for sw1 to sw3, an interrupt request is generated if generation of an interrupt has been allowed (cicr2).
302 chapter 13 comparator figure 13.2-2 comparator block diagram (cosr4) comparator power-on vcc rstx decoder 3 6 battery valid (cosr2) comparator status register 2 alarm 3 o32 o31 o23 o21 battery valid alarm battery p75/vsi2 p74/vol2 valid alarm p86/an1/sw2 o13 o12 p53/aco p54/ofb1 p55/ofb2 p56/ofb3 internal data bus battery selection circuit spm0 (cocr1) comparator control register 1 spm1 spm2 bof1 bof2 bof3 cvrh1 cvrl cvrh2 p70/dcin p77/vsi3 p76/vol3 p87/an2/sw3 p73/vsi1 p85/an0/sw1 p72/vol1 vol vsi sw ofb vol vsi sw ofb vol vsi sw ofb var1 ven1 var2 ven2 var3 ven3 p51/alr2 p52/alr3 p50/alr1 cen4 cen5 cen6 cen1 cen2 cen3 cen7 (cicr2) comparator interrupt control register 2 irq5 irq4 (cicr1) comparator interrupt control register 1 (cosr3) comparator status register 3 8 rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out val1 val2 val3 p71/dcin2 rh rl (voltage in out swr1 swr2 swr3 sen1 sen2 sen3 + - + - + - 3 cen8 xoa x1a watch sws1 dc1 dc2 b1 b2 (cocr2) comparator control register 2 b3 sw sw sw sw sw sw sw sws2 sws3 cor4 cor5 cor6 cor1 cor2 cor3 cor7 cor8 cos4 cos5 cos6 cos1 cos2 cos3 cos7 cos8 (cosr1) comparator + - comparator 1 comparator 2 comparator 3 comparator 4 pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin comparator 2) reset prescaler supervisory circuit 1 supervisory circuit 2 supervisory circuit 3 comparator 5) comparator 6) comparator 7) comparator 8) comparator 3) comparator 4) status register 1 status register 4
303 13.3 pins of the comparator 13.3 pins of the comparator this section describes the pins associated with the comparator. it also shows a block diagram of pins. n pins associated with the comparator the pins associated with the comparator are as follows: p50/alr1, p51/alr2, p52/alr3, p53/aco, p54/ofb1, p55/ofb2, p56/ofb3, p70/dcin, p71/dcin2, p72/vol1, p73/vsi1, p74/vol2, p75/vsi2, p76/vol3, p77/vsi3, p85/an0/sw1, p86/an1/sw2, p87/an2/sw3, cvrh1, cvrh2, cvrl. each of these pins acts as a general-purpose port or a comparator. p50/alr1 to p52/alr3: each of these pins acts as a general-purpose i/o port (p50 to p52) or as an alarm signal output pin (alr1 to alr3) used when the battery charge is running low. p53/aco: this pin acts as a general-purpose i/o port (p53) or as an output pin (aco) used when on/ off of the comparator ac adapter power supply is detected. p54/ofb1 to p56/ofb3: each of these pins acts as a general-purpose i/o port (p54 to p56) or as a battery discharge control signal output pin (ofb1 to ofb3). for "ofb1 to 3" output, discharge is allowed by "l". p85/an0/sw1 to p87/an2/sw3: each of theses pins acts as a general-purpose i/o port (p85 to p87), as an input pin (sw1 to sw3) for the detection of the comparator voltage mount/dismount, or as an a/d input pin. p70/dcin: this pin acts as a general-purpose i/o port (p70) or as an input pin (dcin) for the detection of mount/dismount of the comparator ac adapter power supply. p71/dcin2: each of these pins acts as a general-purpose i/o port (p71) or as an input pin (dcin2) for the detection of mount/dismount of the comparator ac adapter power supply. p72/vol1, p74/vol2, p76/vol3: each of these pins acts as a general-purpose i/o port (p72, p74, p76) or as an input pin (vol1, vol2, vol3) for the detection of battery intermittence. p73/vsi1, p75/vsi2, p77/vsi3: each of these pins acts as a general-purpose i/o port (p73, p75, p77) or as an input pin (vsi1, vsi2, vsi3) for comparator battery remainder monitoring. cvrh1, cvrh2, cvrl: these pins are used as the reference power supply pins for voltage comparators of the comparator. hysteresis characteristics can be attached during voltage comparison, depending on the input voltage level.
304 chapter 13 comparator note: these pins operate as general-purpose ports when the personal computer is activated. to use these pins as a comparator function, use the comparator control register 2 (cocr2) to allow these pins to function for the comparator. n block diagram of pins associated with the comparator figure 13.3-1 block diagram of pins associated with the comparator figure 13.3-2 block diagram of pins associated with the comparator pin p-ch n-ch pdr read pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) ddr (port direction register) stop/watch mode ddr (port direction register) p50/alr1 p51/alr2 p52/alr3 p53/aco p54/ofb1 p55/ofb2 p56/ofb3 internal data bus pdr read from resource output from resource output enable (cocr2) spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions) pin p-ch n-ch pdr read pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) ddr (port direction register) stop/watch mode ddr (port direction register) a/d input enable bit a/d converter to a/d converter analog input comparator input p85/an0/sw1 p86/an1/sw2 p87/an2/sw3 comparator operation comparator internal data bus channel selection bit enable bit (cocr2) control bit (cier) spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
305 13.3 pins of the comparator figure 13.3-3 block diagram of pins associated with the comparator note: the comparator becomes operation enable state, even if the stop mode (spl=1), when the comparator operation was enabled by the comparator control register 2 (cocr2). p70/dcin p71/dcin2 p72/vol1 p73/vsi1 p74/vol2 p75/vsi2 p76/vol3 p77/vsi3 pin p-ch n-ch pdr read pdr write ddr write output latch stop/watch mode (spl=1) pdr (port data register) ddr (port direction register) stop/watch mode ddr (port direction register) comparator input control bit (cier) converter operation enable bit (cocr2) comparator internal data bus spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
306 chapter 13 comparator 13.4 registers of the comparator this section shows the registers associated with the comparator. n registers associated with comparator figure 13.4-1 block diagram of pins associated with the comparator bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xx000000 b initial value r/w r/w r/w cosr2(comparator status register 2) var1 var2 var3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 b initial value r/w r/w r/w cor1 cor2 cor3 cor4 cosr1(comparator status register 1) cor5 cor6 r/w r/w r/w cor7 r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 b initial value r/w r/w r/w cen1 cen2 cen3 cen4 cicr1(comparator interrupt control register 1) cen5 cen6 r/w r/w r/w cen7 r/w -- r/w cor8 cen8 r/w r/w r/w r/w swr1 swr2 swr3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address xx000000 b initial value spm0 spm1 spm2 cocr1(comparator control register 1) bof1 bof2 bof3 0051 h 0052 h r/w r/w r/w r/w r/w r/w -- dc1 dc2 b1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address 0053 h address 0054 h address 0055 h address xxx11111 b initial value cocr2(comparator control register 2) - -- b2 b3 r/w r/w r/w r/w r/w
307 13.4 registers of the comparator r/w : read/write enabled r : read only x : undefined bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xx000000 b initial value ven1 ven2 cicr2(comparator interrupt control register 2) ven3 r/w r/w r/w -- r/w r/w r/w sen1 sen2 sen3 0056 h address 0057 h address 0058 h address 0059 h address die1 die2 bie1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxx11111 b initial value cier(comparator input enable register) - - - bie2 bie3 r/w r/w r/w r/w r/w val1 val2 val3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b initial value cosr3(comparator status register 3) r r r - - r r r sws1 sws3 sws2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b initial value cosr4(comparator status register 4) r r r r r r r r cos2 cos1 cos3 cos4 cos5 cos6 cos7 cos8
308 chapter 13 comparator 13.4.1 comparator control register 1 (cocr1) the comparator control register (cocr1) is used to confirm the sequence setting value for the battery selection circuit and to set discharge control signal output for batteries. n comparator control register 1 (cocr1) figure 13.4-2 comparator control register 1 (cocr1) spm0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address xx000000 b initial value spm1 spm2 r/w - spm2 0 1 0 1 0 1 0 1 spm1 0 0 0 0 1 1 1 1 spm0 0 0 1 1 0 0 1 1 decode output o12 0 0 1 1 0 0 1 0 o13 0 0 1 1 0 1 0 0 o21 0 0 0 0 1 1 0 1 o23 0 0 1 0 1 1 0 0 o31 0 0 0 0 1 0 1 1 o32 0 0 0 1 0 0 1 1 battery sequence parallel discharge battery 1 <-- battery 2 <-- battery 3 battery 1 <-- battery 3 <-- battery 2 battery2 <-- battery 3 <-- battery 1 battery 2 <-- battery 1 <-- battery 3 battery 3 <-- battery 1 <-- battery 2 battery 3 <-- battery 2 <-- battery 1 sequence setting bit bof1 bof2 bof3 r/w r/w r/w r/w r/w bof1 0 1 battery 1 discharge control signal output disabled battery 1 discharge control signal output enabled battery 1 discharge control signal output enable bit bof2 0 1 battery 2 discharge control signal output disabled battery 2 discharge control signal output enabled battery 2 discharge control signal output enable bit bof3 0 1 battery 3 discharge control signal output disabled battery 3 discharge control signal output enabled battery 3 discharge control signal output enable bit - : read/write enabled : read only : undefined : initial value r/w r x h
309 13.4 registers of the comparator reference: when the ofb1 to 3 pin output is "h", battery discharge is disabled. when it is "l", battery discharge is allowed. note: do not rewrite the sequence control bit (cocr1:spm0 to 2) when the comparator is operating. table 13.4-1 function of each bit of the comparator control register 1 (cocr1) bit name function bit 7 bit 6 unused bits ? the read value is undefined. ? writing has no efect on operation. bit 5 bof3: battery 3 discharge control signal output enable bit this bit is used to allow discharge control signal output to battery 3. when "1" is written in this bit, output of discharge control signal is enabled. when "0" is written, output of discharge control signal is disabled. bit 4 bof2: battery 2 discharge control signal output enable bit this bit is used to allow discharge control signal output to battery 2. when "1" is written in this bit, output of discharge control signal is enabled. when "0" is written, output of discharge control signal is disabled. bit 3 bof1: battery 1 discharge control signal output enable bit this bit is used to allow discharge control signal output to battery 1. when "1" is written in this bit, output of discharge control signal is enabled. when "0" is written, output of discharge control signal is disabled. bit 2 bit 1 bit 0 spm2, spm1, somo: sequence setting bit these bits are used to set sequence data for the battery selection circuit. depending on the set value, either parallel discharge or sequential discharge is selected. by reading this bit, the sequence setting value can be confirmed.
310 chapter 13 comparator 13.4.2 comparator control register 2 (cocr2) comparator control register 2 is used to control i/o of the comparator. n comparator control register 2 (cocr2) figure 13.4-3 comparator control register 2 (cocr2) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address xxx11111 b initial value r/w r/w r/w dc1 b1 dc2 -- dc1 0 1 enable dcin comparator and aco output disable dcin comparator operation dc1 control bit dc2 0 1 enable dcin2 comparator operation disable dcin2 comparator operation dc2 control bit b1 0 1 enable operation and output of the comparator used in battery 1 disable operation of the comparator used in battery 1 b1 control bit b2 b3 - b2 0 1 enable operation and output of the comparator used in battery 2 disable operation of the comparator used in battery 2 b2 control bit b3 0 1 enable operation and output of the comparator used in battery 3 disable operation of the comparator used in battery 3 b3 control bit r/w r/w r/w r x : read/write enabled : read only : undefined : initial value h
311 13.4 registers of the comparator table 13.4-2 function of each bit of the comparator control register 2 (cocr2) bit name function bit 7 bit 6 bit 5 unused bits ? the read value is undefined. ? writing has no efect on operation. bit 4 b3: b3 control bit this bit is used to allow comparator operation of the pin used for battery 3. ? when this bit is set to "0", the comparators for the vol3, vsi3, and sw3 pins operate and ofb3 and alr3 pin output is allowed. ? when this bits is set to "1", the comparators for the vol3, vsi3, and sw3 pins stop. ofb3 and alr3 pin output becomes port output. bit 3 b2: b2 control bit this bit is used to allow comparator operation of the pin used for battery 2. ? when this bit is set to "0", the comparators for the vol2, vsi2, and sw2 pins operate and ofb2 and alr2 pin output is allowed. ? when this bits is set to "1", the comparators for the vol2, vsi2, and sw2 pins stop. ofb2 and alr2 pin output becomes port output. bit 2 b1: b1 control bit this bit is used to allow comparator operation of the pin used for battery 1. ? when this bit is set to "0", the comparators for the vol1, vsi1, and sw1 pins operate and ofb1 and alr1 pin output is allowed. ? when this bit is set to "1", the comparators for the vol1, vsi1, and sw1 pins stop. ofb1 and alr1 pin output becomes port output. bit 1 dc2: dc2 control register this bit is used to allow comparator operation of the dc2 pin. ? when this bit is set to "0", the comparator for the dcin2 pin operates ? when this bit is set to "1", the comparator for the dcin2 pin stops. bit 0 dc1: dc1 control bit this bit is used to allow comparator operation of the dc1 pin. ? when this bit is set to "0", the comparator for the dcin pin operates and aco pin output is allowed. ? when this bit is set to "1", the comparator for the dcin pin stops and aco pin output becomes port output.
312 chapter 13 comparator 13.4.3 comparator status register 1 (cosr1) comparator status register 1 (cosr1) holds and stores an edge change in output voltage from the comparator 1 and an out signal output from voltage comparators. this allows change of battery voltage to be confirmed. n comparator status register 1 (cosr1) figure 13.4-4 comparator status register 1 (cosr1) cor1 cor6 cor5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address 00000000 b initial value cor2 cor3 cor7 cor4 cor1 0 1 comparator 1 interrupt request not detected comparator 1 interrupt request bit r/w r/w r/w r/w r/w r/w r/w cor2 0 1 voltage comparator 2 interrupt request not detected voltage comparator 2 interrupt request bit cor3 0 1 voltage comparator 3 interrupt request not detected voltage comparator 3 interrupt request bit cor4 0 1 voltage comparator 4 interrupt request not detected voltage comparator 4 interrupt request bit cor5 0 1 voltage comparator 5 interrupt request not detected voltage comparator 5 interrupt request bit cor6 0 1 voltage comparator 6 interrupt request not detected voltage comparator 6 interrupt request bit cor7 0 1 voltage comparator 7 interrupt request not detected voltage comparator 7 interrupt request bit cor8 r/w cor8 0 1 voltage comparator 8 interrupt request not detected voltage comparator 8 interrupt request bit comparator 1 detected) comparator 1 interrupt request detected (the edge of output from voltage comparator 2 interrupt request detected (the edge of out output from voltage comparator 2 detected) voltage comparator 3 interrupt request detected (the edge of out output from voltage comparator 3 detected) voltage comparator 4 interrupt request detected (the edge of out output from voltage comparator 4 detected) voltage comparator 5 interrupt request detected (the edge of out output from voltage comparator 5 detected) voltage comparator 6 interrupt request detected (the edge of out output from voltage comparator 6 detected) voltage comparator 7 interrupt request detected (the edge of out output from voltage comparator 7 detected) voltage comparator 8 interrupt request detected (the edge of out output from voltage comparator 8 detected) h r/w r : read/write enabled : read only : initial value
313 13.4 registers of the comparator table 13.4-3 comparator status register 1 (cosr1) bit functions bit name function bit 7 cor8: voltage comparator 8 interrupt request bit this bit holds and stores an edge change in out output from voltage comparator 8 (the result of p77/vsi3 pin input comparison by voltage comparator 8). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen8) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect on this bit and does not change the bit. bit 6 cor7: voltage comparator 7 interrupt request bit this bit holds and stores an edge change in out output from voltage comparator 7 (the result of p76/vol3 pin input comparison by voltage comparator 7). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen7) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect and does not change the bit. bit 5 cor6: voltage comparator 6 interrupt request bit 8. this bit holds and stores an edge change in out output from voltage comparator 6 (the result of p75/vsi2 pin input comparison by voltage comparator 6). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen6) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect and does not change the bit. bit 4 cor5: voltage comparator 5 interrupt request bit this bit holds and stores an edge change in out output from voltage comparator 5 (the result of p74/vol2 pin input comparison by voltage comparator 5). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen5) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect and does not change the bit. bit 3 cor4: voltage comparator 4 interrupt request bit this bit holds and stores an edge change in the out output from voltage comparator 4 (the result of p73/vsi1 pin input comparison by voltage comparator 4). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen4) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect and does not change the bit. bit 2 cor3: voltage comparator 3 interrupt request bit 14. this bit holds and stores an edge change in the out output from voltage comparator 3 (the result of p72/vol1 pin input comparison by voltage comparator 3). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen3) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect and does not change the bit.
314 chapter 13 comparator note: to clear each bit, first read data from the bit, then write "0" in it. bit 1 cor2: voltage comparator 2 interrupt request bit this bit holds and stores an edge change in out output from voltage comparator 2 (the result of p71/dcin2 pin input comparison by voltage comparator 2). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen2) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect and does not change the bit. bit 0 cor1: voltage comparator 1 interrupt request bit this bit holds and stores an edge change in out output from voltage comparator 1 (the result of p70/dcin pin input comparison by comparator 1). (this bit is set to "1" when the rising/falling edge of out output is detected. at this time, if the interrupt request enable bit (cicr1:cen1) is "1," an interrupt request is output. this bit is cleared when "0" is written. writing "1" in this bit has no effect and does not change the bit. table 13.4-3 comparator status register 1 (cosr1) bit functions (continued) bit name function
315 13.4 registers of the comparator 13.4.4 comparator interrupt control register 1 (cicr1) comparator interrupt control register 1 (cicr1) is used to allow an interrupt to be generated when the comparator status register 1 (cosr1) holds an edge change. n comparator interrupt control register 1 (cicr1) figure 13.4-5 comparator interrupt control register 1 (cicr1) cen1 cen6 cen5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 4 h address 00000000 b initial value cen2 cen3 cen7 cen4 cen1 0 1 disable comparator 1 interrupt comparator 1 interrupt enable bit r/w r/w r/w r/w r/w r/w r/w cen2 0 1 disable voltage comparator 2 interrupt voltage comparator 2 interrupt enable bit cen3 0 1 disable voltage comparator 3 interrupt voltage comparator 3 interrupt enable bit cen4 0 1 disable voltage comparator 4 interrupt voltage comparator 4 interrupt enable bit cen5 0 1 disable voltage comparator 5 interrupt voltage comparator 5 interrupt enable bit cen6 0 1 disable voltage comparator 6 interrupt voltage comparator 6 interrupt enable bit cen7 0 1 disable voltage comparator 7 interrupt voltage comparator 7 interrupt enable bit cen8 r/w cen8 0 1 disable voltage comparator 8 interrupt voltage comparator 8 interrupt enable bit enable voltage comparator 2 interrupt (an interrupt is generated when a change is detected in voltage comparator 2 output) enable voltage comparator 2 interrupt (an interrupt is generated when a change is detected in voltage comparator 2 output) enable voltage comparator 3 interrupt (an interrupt is generated when a change is detected in voltage comparator 3 output) enable voltage comparator 4 interrupt (an interrupt is generated when a change is detected in voltage comparator 4 output) enable voltage comparator 5 interrupt (an interrupt is generated when a change is detected in voltage comparator 5 output) enable voltage comparator 6 interrupt (an interrupt is generated when a change is detected in voltage comparator 6 output) enable voltage comparator 7 interrupt (an interrupt is generated when a change is detected in voltage comparator 7 output) enable voltage comparator 8 interrupt (an interrupt is generated when a change is detected in voltage comparator 8 output) r/w r x : read/write enabled : read only : undefined : initial value
316 chapter 13 comparator table 13.4-4 comparator interrupt control register 1 (cicr1) bit functions bit name function bit 7 cen8: voltage comparator 8 interrupt enable bit this bit is used to allow an interrupt when a change is detected in comparator 8 out output. when the voltage comparator 8 interrupt request bit (cosr1:cor8) is "1" an interrupt request is posted to the cpu. bit 6 cen7: voltage comparator 7 interrupt enable bit this bit is used to allow an interrupt when a change is detected in voltage comparator 7 out output. when the voltage comparator 7 interrupt request bit (cosr1:cor7) is "1" an interrupt request is posted to the cpu. bit 5 cen6: voltage comparator 6 interrupt enable bit this bit is used to allow an interrupt when a change is detected in voltage comparator 6 out output. when the voltage comparator 6 interrupt request bit (cosr1:cor6) is "1" an interrupt request is posted to the cpu. bit 4 cen5: voltage comparator 5 interrupt enable bit this bit is used to allow an interrupt when a change is detected in voltage comparator 5 out output. when the voltage comparator 5 interrupt request bit (cosr1:cor5) is "1" an interrupt request is posted to the cpu. bit 3 cen4: voltage comparator 4 interrupt enable bit this bit is used to allow an interrupt when a change is detected in voltage comparator 4 out output. when the voltage comparator 4 interrupt request bit (cors1:cor4) is "1" an interrupt request is posted to the cpu. bit 2 cen3: voltage comparator 3 interrupt enable bit this bit is used to allow an interrupt when a change is detected in voltage comparator 3 out output. when the voltage comparator 3 interrupt request bit (cosr1:cor3) is "1" an interrupt request is posted to the cpu. bit 1 cen2: voltage comparator 2 interrupt enable bit this bit is used to allow an interrupt when a change is detected in voltage comparator 2 out output. when the voltage comparator 2 interrupt request bit (cosr1:cor2) is "1" an interrupt request is posted to the cpu. bit 0 cen1: voltage comparator 1 interrupt enable bit this bit is used to allow an interrupt when a change is detected in voltage comparator 1 out output. when the voltage comparator 1 interrupt request bit (cosr1:cor1) is "1" an interrupt request is posted to the cpu.
317 13.4 registers of the comparator 13.4.5 comparator status register 2 (cosr2) comparator status register 2 holds and stores an edge change in comparator output from sw1 to sw3 and in a valid signal from the battery monitoring circuit. this allows the valid status of each battery to be detected. n comparator status register 2 (cosr2) figure 13.4-6 comparator status register 2 (cosr2) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 5 h xx000000 b r/w r/w r/w var1 var3 var2 -- var1 0 1 battery monitoring circuit 1 valid interrupt request not detected battery monitoring circuit 1 valid interrupt request bit var2 0 1 battery monitoring circuit 2 valid interrupt request not detected battery monitoring circuit 2 valid interrupt request bit var3 0 1 battery monitoring circuit 3 valid interrupt request not detected battery monitoring circuit 3 valid interrupt request bit swr1 swr2 swr3 swr1 0 1 comparator 2 (sw1) interrupt request not detected comparator 2(sw1) interrupt request bit swr2 0 1 comparator 3 (sw2) interrupt request not detected comparator 3(sw2) interrupt request bit swr3 0 1 comparator 4 (sw3) interrupt request not detected comparator 4(sw3) interrupt request bit r/w r/w r/w address initial value battery monitoring circuit 1 valid interrupt request detected comparator 2 (sw1) interrupt request detected (the edge of valid output detected) battery monitoring circuit 2 valid interrupt request detected (the edge of valid output detected) battery monitoring circuit 3 valid interrupt request detected (the edge of valid output detected) (the edge of sw1 output detected) comparator 3 (sw2) interrupt request detected (the edge of sw2 output detected) comparator 4 (sw3) interrupt request detected (the edge of sw3 output detected) r/w r x : read/write enabled : read only : undefined : initial value
318 chapter 13 comparator note: to clear each bit, first read data from the bit then write "0" in it. table 13.4-5 comparator status register 2 (cosr2) bit functions bit name function bit 7 bit 6 unused bits ? the read value is undefined. ? writing has no efect on operation. bit 5 swr3: comparator 4 interrupt request bit this bit is set to "1" when an edge change is detected in comparator 4 output (the results of p87/sw3 pin input comparison by comparator 4). when this bit and the sw3 interrupt enable bit (cicr2:sen3) are "1" an interrupt request is output. this bit is cleared by writing "0" in it. writing "1" in this bit has no effect and does not change the bit. bit 4 swr2: comparator 3 interrupt request bit this bit is set to "1" when an edge change is detected in comparator 3 output (the results of p86/sw2 pin input comparison by comparator 4). when this bit and the sw2 interrupt enable bit (cicr2:sen2) are "1" an interrupt request is output. this bit is cleared by writing "0" in it. writing "1" in this bit has no effect and does not change the bit. bit 3 swr1: comparator 2 interrupt request bit this bit is set to "1" when an edge change is detected in comparator 2 output (the results of p85/sw1 pin input comparison by comparator 4). when this bit and the sw1 interrupt enable bit (cicr2:sen1) are "1," an interrupt request is output. this bit is cleared by writing "0" in it. writing "1" in this bit has no effect and does not change the bit. bit 2 var3: battery monitoring circuit 3 valid interrupt request bit this bit is set to "1" when a change is detected in battery monitoring circuit 3 valid output. when this bit and the battery monitoring circuit 3 valid interrupt enable bit (cicr2:ven3) are "1," an interrupt request is output. this bit is cleared by writing "0" in it. writing "1" in this bit has no effect and does not change this bit. bit 1 var2: battery monitoring circuit 2 valid interrupt request bit this bit is set to "1" when a change is detected in battery monitoring circuit 2 valid output. when this bit and the battery monitoring circuit 2 valid interrupt enable bit (cicr2:ven2) are "1," an interrupt request is output. this bit is cleared by writing "0" in it. writing "1" in this bit has no effect and does not change the bit. bit 0 var1: battery monitoring circuit 1 valid interrupt request bit this bit is set to "1" when a change is detected in battery monitoring circuit 1 valid output. when this bit and the battery monitoring circuit 1 valid interrupt enable bit (cicr2:ven1) are "1," an interrupt request is output. this bit is cleared by writing "0" in it. writing "1" in this bit has no effect and does not change the bit.
319 13.4 registers of the comparator 13.4.6 comparator interrupt control register (cicr2) comparator interrupt control register 2 (cicr2) is used to allow interrupt generation when an edge change is seized by the comparator status register 2 (cosr2). n comparator interrupt control register 2 (cicr2) figure 13.4-7 comparator interrupt control register 2 (cicr2) ven3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 6 h xx000000 b ven1 - ven2 - ven1 0 1 disable power supply monitoring circuit 1 valid interrupt enable power supply monitoring circuit 1 valid interrupt allowed disable power supply monitoring circuit 3 valid interrupt enable power supply monitoring circuit 3 valid interrupt allowed disable power supply monitoring circuit 2 valid interrupt enable power supply monitoring circuit 2 valid interrupt allowed power supply monitoring circuit 1 valid interrupt enable bit ven2 0 1 power supply monitoring circuit 2 valid interrupt enable bit ven3 0 1 power supply monitoring circuit 3 valid interrupt enable bit r/w r/w r/w sen3 sen2 sen1 r/w r/w r/w sew1 0 1 disable comparator 2 (sw1) interrupt enable comparator 2 (sw1) interrupt disable comparator 3 (sw2) interrupt enable comparator 3 (sw2) interrupt disable comparator 4 (sw3) interrupt enable comparator 4 (sw3) interrupt comparator 2 (sw1) interrupt enable bit sew2 0 1 comparator 3 (sw2) interrupt enable bit sew3 0 1 comparator 4 (sw3) interrupt enable bit address initial value r/w r x : read/write enabled : read only : undefined : initial value
320 chapter 13 comparator table 13.4-6 comparator interrupt control register 2 (cicr2) bit functions bit name function bit 7 bit 6 unused bits ? the read value is undefined. ? writing has no efect on operation. bit 5 sw3: comparator 4 interrupt enable bit this bit is used to allow a comparator 4 interrupt. if this bit is set to "1," an interrupt to the cpu will be generated when the comparator 4 interrupt request bit is set to "1" (cosr2:sw3=1). bit 4 sw2: comparator 3 interrupt enable bit this bit is used to allow a comparator 3 interrupt. if this bit is set to "1," an interrupt to the cpu will be generated when the comparator 3 interrupt request bit is set to 1" (cosr2:sw2=1). bit 3 sw1: comparator 2 interrupt enable bit this bit is used to allow a comparator 2 interrupt. if this bit is set to "1," an interrupt to the cpu will be generated when the comparator 2 interrupt request bit is set to 1" (cosr2:sw1=1). bit 2 ven3: battery monitoring circuit 3 valid interrupt enable bit this bit is used to allow a battery monitoring circuit 3 valid interrupt. if this bit is set to "1," an interrupt to the cpu will be generated when the battery monitoring circuit 3 interrupt request bit is set to "1" (cosr2:var3=1). bit 1 ven2: battery monitoring circuit 2 valid interrupt enable bit this bit is used to allow a battery monitoring circuit 2 valid interrupt. if this bit is set to "1," an interrupt to the cpu will be generated when the battery monitoring circuit 2 interrupt request bit is set to "1" (cosr2:var2=1). bit 0 ven1: battery monitoring circuit 1 valid interrupt enable bit this bit is used to allow a battery monitoring circuit 1 valid interrupt. if this bit is set to "1," an interrupt to the cpu will be generated when the battery monitoring circuit 1 interrupt request bit is set to "1" (cosr2:var1=1).
321 13.4 registers of the comparator 13.4.7 comparator status register 3 (cosr3) comparator status register 3 stores comparator output from sw1 to sw3 and a valid signal from the battery monitoring circuit. the status of each battery can be confirmed by reading this register. n comparator status register 3 (cosr3) figure 13.4-8 comparator status register 3 (cosr3) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 7 h xxxxxxxx b rrr - - val3 val1 val2 sws3 sws2 sws1 r r r val1 0 1 battery 1 invalid battery 1 valid battery 1 valid status confirmation bit val2 0 1 battery 2 invalid battery 2 valid battery 2 valid status confirmation bit val3 0 1 battery 3 invalid battery 3 valid comparator 2 (sw1) status confirmation bit sws1 0 1 sws2 0 1 sws3 0 1 battery 3 valid status confirmation bit battery 1 not connected battery 1 connected comparator 3 (sw2) status confirmation bit battery 2 not connected battery 2 connected comparator 4 (sw3) status confirmation bit battery 3 not connected battery 3 connected address initial value r/w r x : read/write enabled : read only : undefined
322 chapter 13 comparator table 13.4-7 comparator status register 3 (cosr3) bit functions bit name function bit 7 bit 6 unused bits ? the read value is undefined. ? writing has no efect on operation. bit 5 sws3: comparator 4 status confirmation bit read this bit to confirm the output value from comparator 4. when this bit is "1", it indicates the battery is connected. when this bit is "0", it indicates the battery is not connected. writing in this bit has no effect. bit 4 sws2: comparator 3 status confirmation bit read this bit to confirm the output value from comparator 3. when this bit is "1", it indicates the battery is connected. when this bit is "0", it indicates the battery is not connected. writing in this bit has no effect. bit 3 sws1: comparator 2 status confirmation bit read this bit to confirm the output value from comparator 2. when this bit is "1", it indicates the battery is connected. when this bit is "0", it indicates the battery is not connected. writing in this bit has no effect. bit 2 val3: battery 3 valid status confirmation bit 3 read this bit to confirm the valid signal output value from battery monitoring circuit 3. when this bit is "1", it indicates battery 3 is valid. when this bit is "0", it indicates battery 3 is invalid. writing in this bit has no effect. bit 1 val2: battery 2 valid status confirmation bit 2 read this bit to confirm the valid signal output value from battery monitoring circuit 2. when this bit is "1", it indicates battery 2 is valid. when this bit is "0", it indicates battery 2 is invalid. writing in this bit has no effect. bit 0 val1: battery 1 valid status confirmation bit 1 read this bit to confirm the valid signal output value from battery monitoring circuit 1. when this bit is "1", it indicates battery 1 is valid. when this bit is "0", it indicates battery 1 is invalid. writing in this bit has no effect.
323 13.4 registers of the comparator 13.4.8 comparator status register 4 (cosr4) comparator status register 4 (coisr4) stores output from comparator 1 and the out signals that are output from the battery monitoring circuits. the status of each battery can be confirmed by reading this register. n comparator status register 4 (cosr4) figure 13.4-9 comparator status register 4 (cosr4) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 8 h xxxxxxxx b rrr cos8 cos7 cos3 cos1 cos2 cos6 cos5 cos4 r r r cos1 0 1 comparator 1 output l comparator 1 output h comparator status confirmation bit 1 cos2 0 1 comparator status confirmation bit 2 cos3 0 1 comparator status confirmation bit 4 cos4 0 1 cos5 0 1 comparator status confirmation bit 3 sws6 0 1 comparator status confirmation bit 6 r r sws7 0 1 comparator status confirmation bit 7 sws8 0 1 comparator status confirmation bit 8 comparator status confirmation bit 5 voltage comparator 2 output l voltage comparator 2 output h voltage comparator 3 output l voltage comparator 3 output h voltage comparator 4 output l voltage comparator 4 output h voltage comparator 5 output l voltage comparator 5 output h voltage comparator 6 output l voltage comparator 6 output h voltage comparator 7 output l voltage comparator 7 output h voltage comparator 8 output l voltage comparator 8 output h address initial value r/w r x : read/write enabled : read only : undefined
324 chapter 13 comparator table 13.4-8 comparator status register 4 (cosr4) bit functions bit name function bit 7 cos8: comparator status confirmation bit 8 reading this bit to confirm out output from voltage comparator 8. when this bit is "1", it indicates the power level of battery 3 is enough. when this bit is "0", it indicates the power level of battery 3 is in short. bit 6 cos7: comparator status confirmation bit 7 reading this bit to confirm out output from voltage comparator 7. when this bit is "1", it indicates power is being supplied from battery 3. when this bit is "0", it indicates power supply from battery 3 has dropped. bit 5 cos6: comparator status confirmation bit 6 reading this bit to confirm out output from voltage comparator 6. when this bit is "1", it indicates the power level of battery 2 is enough. when this bit is "0", it indicates the power level of battery 2 is in short. bit 4 cos5: comparator status confirmation bit 5 read this bit to confirm out output from voltage comparator 5. when this bit is "1", it indicates power is being supplied from battery 2. when this bit is "0", it indicates power supply from battery 2 has dropped. bit 3 cos4: comparator status confirmation bit 4 read this bit to confirm out output from voltage comparator 4. when this bit is "1", it indicates the power level of battery 1 is enough. when this bit is "0", it indicates the power level of battery 1 is in short. bit 2 cos3: comparator status confirmation bit 3 reading this bit to confirm out output from voltage comparator 3. when this bit is "1", it indicates power is being supplied from battery 1. when this bit is "0", it indicates power supply from battery 1 has dropped. bit 1 cos2: comparator status confirmation bit 2 read this bit to confirm out output from voltage comparator 2. when this bit is "1", it indicates power is being supplied from the ac adapter connected to dcin2. when this bit is "0", it indicates power supply from the ac adapter connected to dcin2 has dropped. bit 0 cos1: comparator status confirmation bit 1 read this bit to confirm out output from voltage comparator 1. when this bit is "1", it indicates power is being supplied from the ac adapter connected to dcin. when this bit is "0", it indicates power supply from the ac adapter connected to dcin has dropped.
325 13.4 registers of the comparator 13.4.9 comparator input allow register (cier) comparator input enable register is used to cut the dc path when the comparator is used. n comparator input enable register (cier) figure 13.4-10 comparator input enable register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 9 h xxx11111 b r/w r/w r/w die1 bie1 die2 -- die1 0 1 disable dcin pin comparator input (enable p70 port input) disable dcin pin comparator input (disable p70 port input) dc1 control bit die2 0 1 disable dcin2 pin comparator input (enable p71 port input) enable dcin2 pin comparator input (disable p71 port input) dc2 control bit bie1 0 1 disable vsi1/vol1/sw1 pin comparator input (enable p73/p72/p85 port input) enable vsi1/vol1/sw1 pin comparator input (disable p73/p72/p85 port input) b1 control bit bie2 bie3 - bie2 disable vsi2/vol2/sw2 pin comparator input (enable p75/p74/p86 port input) enable vsi2/vol2/sw2 pin comparator input (disable p75/p74/p86 port input) b2 control bit bie3 disable vsi3/vol3/sw3 pin comparator input (enable p77/p76/p87 port input) enable vsi3/vol3/sw3 pin comparator input (disable p77/p76/p87 port input) b3 control bit r/w r/w 0 1 0 1 address initial value r/w r x : read/write enabled : read only : undefined : initial value
326 chapter 13 comparator table 13.4-9 comparator input enable register (cier) bit functions bit name function bit 7 bit 6 bit 5 unused bits ? the read value is undefined. ? writing has no efect on operation. bit 4 bie3: b3 control bit this bit is used to allow input from the vol3/vsi3/sw3 pin to the comparator. ? by setting "1" in this bit, the dc path can be cut when the intermediate level is input to the general-purpose port. ? to use the corresponding port as a general-purpose port, set "0" in this bit. bit 3 bie2: b2 control bit this bit is used to allow input from the vol2/vsi2/sw2 pin to the comparator. ? by setting "1" in this bit, the dc path can be cut when the intermediate level is input to the general-purpose port. ? to use the corresponding port as a general-purpose port, set "0" in this bit. bit 2 bie1: b1 control bit this bit is used to allow input from the vol1/vsi1/sw1 pin to the comparator. ? by setting "1" in this bit, the dc path can be cut when the intermediate level is input to the general-purpose port. ? to use the corresponding port as a general-purpose port, set "0" in this bit. bit 1 die2: dc2 control bit this bit is used to allow input from the dcin2 pin to the comparator. ? by setting "1" in this bit, the dc path can be cut when the intermediate level is input to the general-purpose port. ? to use the corresponding port as a general-purpose port, set "0" in this bit. bit 0 die1: dc1 control bit this bit allows input from the dcin pin to the comparator. ? by setting "1" in this bit, the dc path can be cut when the intermediate level is input to the general-purpose port. ? et "0" in the bit to use the corresponding port as a general-purpose port.
327 13.5 comparator interrupts 13.5 comparator interrupts there are 14 different causes for comparator interrupts: ? comparator 1, voltage comparators 2 to 8 interrupts ? batteries 1 to 3 valid interrupts. comparators 2 to 4 interrupts n comparator 1, voltage comparators 2 to 7 interrupts voltage input to the p70/dcin, p71/dcin2, p72/vol1, p73/vsi1, p74/vol2, p75/vs12, p76/ vol3, and p77/vsi3 pins is compared by comparator 1 and voltage comparators 2 to 8 (which have reference voltage input from the cvrh1 and cvrl pins, as hysteresis width). if a change is detected in the output of these comparators (edge detection), the interrupt request bits for comparator 1 and voltage comparators 2 to 8 (cosr1:cor1 to cor8) are set to "1". at this time, if the interrupt enable bit for the comparator 1 and voltage comparators 2 to 8 has been set to "enabled" (cicr1:"cen to cen8"=1), an interrupt request (irq4) to the cpu is generated. in the interrupt processing routine, write "0" in the interrupt enable bits for comparator 1 and voltage comparators 2 to 8 to clear the interrupt requests. n batteries 1 to 3 valid interrupts the battery valid interrupt request bits (cosr2:var1 to var3) are set to "1" under the following conditions: ? in comparison of voltage input to the p72/vol1, p73/vsi1, and p84/an0/sw1 pins by the battery monitoring circuit 1, a change has been detected in the valid output result (edge detection). ? in comparison of voltage input to the p74/vol2, p75/vsi2, and p85/an1/sw2 pins by the battery monitoring circuit 2, a change has been detected in the valid output result (edge detection). ? in comparison of voltage input to the p76/vol3, p77/vsi3, and p86/an2/sw3 pins by the battery monitoring circuit 3, a change has been detected in the valid output result (edge detection). when any of the above conditions is true, an interrupt request (irq5) to the cpu is generated if the battery valid interrupt enable bit has been set to enabled.(cicr2:ven1 to ven3) write "0" in the battery interrupt request bits (cosr2:var1 to var3) in the interrupt processing routine to clear the interrupt requests. n comparators 2 to 4 interrupts voltage input to the p85/an0/sw1, p86/an1/sw2, and p87/an2/sw3 pins is compared by comparators 2 to 4. if a change is detected in the output of these comparators (edge detection), an interrupt request (irq5) to the cpu is generated if the interrupt enable bits for comparators 2 to 4 have been set to "enabled" (cicr2: sen1 to sen3=1). in the interrupt processing routine, write "0" in the interrupt enable bits for comparator 1 and voltage comparators 2 to 8 to clear the interrupt requests.
328 chapter 13 comparator n registers and vector tables associated with comparator interrupts for interrupt operation, see section 3.4.2 "interrupt processing". table 13.5-1 registers and vector tables associated with comparator interrupts interrupt name interrupt level setting register vector table address register bit to be set upper lower irq4 ilr2 (007c h ) l41 (bit 1) l40 (bit 0) fff2 h fff3 h irq5 ilr2 (007c h ) l51 (bit 3) l50 (bit 2) fff0 h fff1 h
329 13.6 operation of the parallel discharge control 13.6 operation of the parallel discharge control this section describes operation in parallel discharge control. n operation of the parallel discharge control to operate in parallel discharge control, setting shown in figure 13.6-1 "setting for parallel discharge control" is required. figure 13.6-1 setting for parallel discharge control in parallel discharge control, discharge is allowed for all batteries unless power is not being supplied from the ac adapter. if power is being supplied from the ac adapter, enable/disable of battery discharge is controlled by the battery discharge control signal output enable bits (cocr1: bof1 to bof3). figure 13.6-2 "circuit for parallel discharge" shows the circuit for parallel discharge. figure 13.6-2 circuit for parallel discharge spm0 (cocr1) comparator control register 1 spm1 spm2 bof1 bof2 bof3 00 0 dc1 (cocr2) comparator control register 2 dc2 b1 b2 b3 : bit to be used 1 : "1" setting 0 : "0" setting p70/dcin + - p53/aco p54/ofb1 p55/ofb2 p56/ofb3 cvrl spm0 (cocr)comparator control register spm1 spm2 bof1 bof2 bof3 pin pin pin pin pin pin
330 chapter 13 comparator 13.7 operation of the sequential discharge control this section describes operation in sequential discharge control. n operation of the sequential discharge control the setting shown in figure 13.7-1 "setting for sequential discharge control" is required to perform the operation in the sequential discharge control. figure 13.7-1 setting for sequential discharge control in sequential discharge control, discharge is controlled in the order that is set by the sequence setting bits (cocr1:spm0 to spm2) when power is not being supplied from the ac adapter. also, discharge can forcibly be allowed by the battery discharge control signal output enable bits (cocr1:bof1 to bof3) even if power is being supplied from the ac adapter. 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 battery sequence battery1 <- battery2 <- battery3 battery1 <- battery3 <- battery2 battery2 <- battery3 <- battery1 battery2 <- battery1 <- battery3 battery3 <- battery1 <- battery2 battery3 <- battery2 <- battery1 spm0 spm1 spm2 bof1 bof2 bof3 dc1 dc2 b1 b2 b3 : bit to be used 1 : "1" setting 0 : "0" setting (cocr1) comparator control register 1 (cocr2) comparator control register 2 spm0 spm1 spm2
331 13.8 sample application 13.8 sample application this section shows an example of a comparator application. n sample application figure 13.8-1 sample application ac adapter power-on reset vcc pin rstx pin battery supervisory circuit 1 valid alarm battery supervisory circuit 3 valid alarm battery supervisory circuit 2 vsi2 pin vol2 pin valid alarm an1/sw2 pin aco ofb1 pin ofb2 pin ofb3 pin vsi3 pin vol3 pin an2/sw3 pin vsi1 pin an0/sw1 pin vol1 pin vol vsi sw ofb vol vsi sw ofb vol vsi sw ofb alr2 pin alr3 pin alr1 pin (voltage comparator) (voltage comparator) (comparator) (voltage comparator) (voltage comparator) (comparator) (voltage comparator) (voltage comparator) (comparator) (voltage comparator) dcin pin dcin2 pin (voltage comparator) mb89570 series pin ac + additional batteries a/d converter additional batteries 1 additional batteries 2 reset ic dc-dc battery selection circuit host controller (battery 2) (battery 3) (battery 1) built-in battery
332 chapter 13 comparator
333 chapter 14 uart/sio this chapter describes the functions and operations of the uart/sio. 14.1 "overview of the uart/sio" 14.2 "configuration of the uart/sio" 14.3 "pins of the uart/sio" 14.4 "registers of the uart/sio" 14.5 "uart/sio interrupt" 14.6 "operation of the uart/sio" 14.7 "operation of the operation mode 0" 14.8 "operation of the operation mode 1"
334 chapter 14 uart/sio 14.1 overview of the uart/sio the uart/sio is a general-purpose serial data communication interface. variable- length serial data can be transferred in clock synchronous or asynchronous mode. the nrz transfer format is adopted and the transfer rate can be set with the dedicated baud rate generator, the external clock, or the internal timer. n functions of uart/sio the uart/sio functions to transmit/receive serial data (serial i/o) to/from other cpus and peripheral devices. ? its full-duplex double buffer allows bidirectional transmission in full-duplex mode. ? a synchronous transfer mode or asynchronous transfer mode can be selected. ? with the built-in baud rate generator, 14 types of baud rates can be selected. in addition, free baud rates can be set using the externally input clock. ? the data length is variable. seven to eight bits can be set when a parity bit is not attached, and eight to nine bits can be set when a parity bit is attached (see table 14.1-1 "operation mode of uart/sio"). ? the nrz (non return to zero) method is adopted as the data transfer format. table 14.1-1 operation mode of uart/sio operation mode data length synchronous mode stop bit length no parity with parity 0 78 asynchronous 1 bit or 2 bits 89 1 8 synchronous C
335 14.2 configuration of the uart/sio 14.2 configuration of the uart/sio the uart/sio consists of the following six blocks. ? serial mode control register 1 (smc1) ? serial mode control register 2 (smc2) ? port generator reload register (src) ? serial status and data register (ssd) ? serial input data register (sidr) ? serial output data register (sodr) n block diagram of uart/sio figure 14.2-1 uart/sio block diagram internal data bus reload reload data register 8-bit counter brge selector p40/uck1 divide by 8 md bit registers parity generator reception counter start bit detection reception state evaluating circuit received data register shifter pin irq6 p41/sda3/ui1 per ovf fer rdrf rie tdre tie cl sbl md transmission counter transmission start circuit tdp,pen txe transmission data register shifter scke txoe parity generator tdre p40/scl3/uck1 p65/uo1
336 chapter 14 uart/sio m serial mode control register 1 (smc1) a register to control the operation mode of the uart/sio. this register sets the presence/ absence of parity, stop bit length, operation mode (data length), synchronous/asynchronous mode, and serial clock. m serial mode control register 2 (smc2) a register to control the operation mode of the uart/sio. this register sets the permission/ prohibition of serial clock output, permission/prohibition of serial data output, switching between the serial port and the general-purpose port, and permission/prohibition of interrupts. m baud rate generator reload register (src) a register to control the uart/sio data transfer rate (baud rate). m serial status and data register (ssd) a register that indicates the state of transmission/reception of the uart/sio and errors. m serial input data register (sidr) a register that holds received data. serial input is converted and stored in this register. m serial output data register (sodr) a register that sets transmission data. the data written to this register is converted into serial data and output.
337 14.3 pins of the uart/sio 14.3 pins of the uart/sio this section shows the pins related to the uart/sio and shows a block diagram of the pins. n pins related to the uart/sio the pins related to uart/sio include the clock i/o pin (p40/scl3/uck1), the serial data output pin (p65/u01), and the serial data input pin (p41/sda3/ui1). all of which can be switched by the bridge circuit selection register (brsr3) and the operating port selection bit (smc2: scke). p40/scl3/uck1 pin the p40/scl3/uck1 pin serves as a general-purpose i/o port (p40), a clock i/o pin (hysteresis input) of the uart/sio (uck1), and the clock line of the i 2 c bus (scl3). when clock output is permitted (smc2: scke = 1), this pin serves as a clock i/o pin of the uart/ sio (uck1) irrespective of the value of the corresponding port direction register. at this time, do not select the external clock (smc1: clk2. clk1, clk0 is other than 100 b ). when this pin is used as a clock input pin of the uart/sio, prohibit clock output (smc: scke = 0) and set it to hiz with the corresponding port data register (pdr4: bit0 = 1). also at this time, select the external clock (smc1: clk2. clk1, clk0 = 100 b ). p65/u01 the p65/u01 pin serves as a general-purpose i/o port (p65) and a serial data output pin of the uart/sio (u01). when serial data output is permitted (smc2: txoe = 1), this pin serves as a serial data output pin of the uart/sio (u01) irrespective of the value of the corresponding port direction register. p41/sda3/ui1 pin the p41/sda3/ui1 pin serves as a general-purpose i/o port (p41), a serial data input pin (hysteresis input) of the uart/sio (uck1), and the data line of the i 2 c bus (sda3). when this pin is used as a serial data input pin of the uart/sio, set it to hiz with the corresponding port data register (pdr4: bit1 = 1).
338 chapter 14 uart/sio n block diagram of pins related to uart/sio figure 14.3-1 block diagram of pins related to uart/sio figure 14.3-2 block diagram of pins related to uart/sio when the uart/sio function is used, p33/uck and p35/u0 must be pulled up externally. i 2 c output multi-address i 2 c output i 2 c input from bridge circuit from bridge circuit from bridge circuit multi-address i 2 c input from bridge circuit output tr. uart input uart output (p40 only) p40/scl3/uck1 p41/sda3/ui1 pin pin pdr read pdr read (for bit manipulation instructions) pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus stop/watch mode stop/watch mode stop/watch mode spl: pin state designate bit of the standby control register (stbc) n-ch from resource (lcd) output enable bit from resource (lcd) output uart output p65/uo1 from bridge circuit pin pdr read pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus stop/watch mode spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
339 14.4 registers of the uart/sio 14.4 registers of the uart/sio this section shows the registers related to the uart/sio. n registers related to uart/sio figure 14.4-1 registers related to uart/sio md tdp sbl bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 0 h address 00000000 b initial value address initial value address initial value address initial value address initial value address initial value r/w pen cl clk1 clk0 clk2 r/w r/w r/w r/w r rr r rr r/w r/w brge bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 b txoe rie tie scke r/w r/w rerc rxe txe -- per ove fer rdrf tdre - r/w r/w w r/w r r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 2 h 00001xxx b rr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 3 h xxxxxxxx b smc1 (serial mode control register 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 3 h xxxxxxxx b w ww w ww w w sodr (serial output data register) sidr (serial input data register) smc2 (serial mode control register 2) ssd (serial status and data register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 4 h xxxxxxxx b src (baud rate generator reload register) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w w r rr 0 0 1 1 h r/w : read/write enabled r : read only w : write only x : undefined
340 chapter 14 uart/sio 14.4.1 serial mode control register 1 (smc1) the serial mode control register 1 (smc1) controls the operation mode of the uart/ sio. this register sets the presence/absence of parity, stop bit length, operation mode (data length), synchronous/asynchronous mode, and serial clock. n serial mode control register 1 (smc1) figure 14.4-2 serial mode control register 1 (smc1) r/w : read/write enabled x : undefined : initial value 2-instruction cycle (0.8 s/10mhz) 8-instruction cycle (3.2 s/10mhz) 32-instruction cycle (12.8 s/10mhz) dedicated baud rate generator - md 0 1 clock asynchronous mode (uart) clock synchronous mode (sio) mode control bit sbl 0 1 1-bit length 2-bit length stop bit length control bit pen 0 1 no parity with parity parity control bit md tdp sbl bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 0 h address 00000000 b initial value r/w pen cl clk1 clk0 clk2 r/w r/w r/w r/w r/w r/w r/w clk2 0 0 0 0 1 clock selection bit clk1 clk0 0 0 1 1 0 0 1 0 1 0 cl 0 1 7-bit length 8-bit length character bit length control bit tdp 0 1 even parity odd parity parity polarity bit
341 14.4 registers of the uart/sio table 14.4-1 functions of each bit in serial mode control register 1 (smc1) bit name function bit 7 md: mode control bit ? this bit specifies the operation mode of the uart/sio. in asynchronous mode, the uart/sio operates with the serial clock divided by eight. in clock synchronous mode, the uart/sio operates with the selected serial clock. bit 6 pen: parity control bit ? this bit specifies whether there is parity in clock asynchronous mode. bit 5 tdp: parity polarity bit ? this bit specifies the parity data attached at the time of serial transmission in clock asynchronous mode. at the time of serial reception, this bit checks the parity data. bit 4 sbl: stop bit length control bit ? this bit specifies the stop bit length in clock asynchronous mode. at the time of serial transmission, this bit attaches a stop bit of the specified bit length. at the time of serial reception, this bit evaluates the stop bit with one bit length irrespective of the set value. bit 3 cl: character bit length control bit ? this bit specifies the character bit length in clock asynchronous mode. bit 2 bit 1 bit 0 clk2 clk1 clk0: clock selection bits ? these bits select a serial clock.
342 chapter 14 uart/sio 14.4.2 serial mode control register 2 (smc2) the serial mode control register 2 (smc2) controls the operation mode of the uart/ sio. this register sets the permission/prohibition of serial clock output, permission/ prohibition of serial data output, switching between the serial port and the general- purpose port, and permission/prohibition of interrupts. n serial mode control register 2 (smc2) figure 14.4-3 serial mode control register 2 (smc2) txoe 0 1 serial data input (available as a port) permits serial data output serial data output bit scke 0 1 clock input (available as a port) permits clock output serial clock output bit brge 0 1 stops baud rate generator starts baud rate generator baud rate generator start bit brge bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 1 h address 00000000 b initial value txoe rie tie scke r/w r/w rerc rxe txe r/w r/w w r/w r/w w tie 0 1 disables transmission interrupts enables transmission interrupts transmission interrupt enable bit rie 0 1 disables reception interrupts enables reception interrupts reception interrupt enable bit txe 0 1 prohibits transmitting operation permits transmitting operation transmission operation enable bit rxe 0 1 prohibits receiving operation permitsreceiving operation reception operation enable bit rerc 0 1 clears each error flag no change and no effect on others received error flag clear bit r/w : read/write enabled w : write only x : undefined : initial value
343 14.4 registers of the uart/sio table 14.4-2 functions of each bit in serial mode control register 2 (smc2) bit name function bit 7 rerc: received error flag clear bit ? when "0" is written to this bit, each error flag (per/ovr/ fer) in the ssd register is cleared. in read cycle, the value is always "1." bit 6 rxe: receiving operation enable bit ? this bit permits the reception of serial data. when "0" is written to this bit during a receiving operation, the operation stops after data reception is completed and the receiving operation is prohibited. bit 5 txe: transmitting operation enable bit ? this bit permits the transmission of serial data. when "0" is written to this bit during a transmitting operation, the operation stops after data transmission is completed and the transmitting operation is prohibited. bit 4 brge: baud rate generator start bit ? this bit starts the baud rate generator. bit 3 txoe: serial data output bit ? this bit controls the permission/prohibition of serial data output. bit 2 scke: serial clock output bit ? this bit controls the i/o of the serial clock in clock synchronous mode. to enter the external clock into the p40/uck pin, set it to input (pdr4: bit0 = 1). bit 1 rie: reception interrupt enable bit ? this bit enables reception interrupts. if reception interrupts are enabled when the rdrf bit is "1" or when each error flag is "1," a reception interrupt occurs immediately. bit 0 tie: transmission interrupt enable bit ? this bit enables transmission interrupts. if transmission interrupts are enabled when the tdre bit is "1," a transmission interrupt occurs immediately.
344 chapter 14 uart/sio 14.4.3 baud rate generator reload register (src) the baud rate generator reload register (src) controls the uart/sio data transfer rate (baud rate). n baud rate generator reload register (src) figure 14.4-4 baud rate generator reload register (src) when the clock selection bits clk2-clk0 are set to "011," the dedicated baud rate generator is selected as a serial clock. with this register, clocks of any baud rate can be set. a value can be written to this register only when the uart is stopped. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 4 h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
345 14.4 registers of the uart/sio 14.4.4 serial status and data register (ssd) the serial status and data register (ssd) indicate the state of transmission/reception of the uart/sio and errors. n serial status and data register (ssd) figure 14.4-5 serial status and data register (ssd) -- per ove fer rdrf tdre - r r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 2 h address 00001xxx b initial value r rr ove 0 1 no overrun error overrun error is present overrun error flag fer 0 1 no framing error framing error is present framing error flag tdre 0 1 transmission data is written vacant transmission data register empty per 0 1 no parity error parity error is present parity error flag rdrf 0 1 vacant received data is written received data register full r/w : read/write enabled r : read only x : undefined : initial value
346 chapter 14 uart/sio table 14.4-3 functions of each bit in serial status and data register (ssd) bit name function bit 7 per: parity error flag ? this bit is set if a parity error occurs during reception and is cleared when "0" is written to the rerc bit in the smc2 register. when this flag is set, the data in sidr becomes invalid. if the per bit is set when the rie bit is set to "1," an interrupt occurs. bit 6 ove: overrun error flag ? this bit is set if an overrun error occurs during reception and is cleared when "0" is written to the rerc bit in the smc2 register. when this flag is set, the data in sidr becomes invalid. if the ove bit is set when the rie bit is set to "1," an interrupt occurs. bit 5 fer: framing error flag ? this bit is set if an framing error occurs during reception and is cleared when "0" is written to the rerc bit in the smc2 register. when this flag is set, the data in sidr becomes invalid. if the fer bit is set when the rie bit is set to "1," an interrupt occurs. bit 4 rdrf: received data register full ? this bit is a flag indicating the state of the received data register (sidr). this bit is set when the received data is loaded to the sidr register and is cleared when the sidr register is read. if the rdrf bit is set when the rie bit is set to "1," an interrupt occurs. bit 3 tdre: transmission data register empty ? this bit is a flag indicating the state of the serial transmission data register (sodr). this bit is cleared when the transmission data is written to the sodr register and is set when the data is loaded to the shifter for transmission and transmission of the data starts. if the tdre bit is set, an interrupt occurs. bit2 bit1 bit0 unused bits ? the read value is undefined. ? writing has no effect on operation.
347 14.4 registers of the uart/sio 14.4.5 serial input data register (sidr) the serial input data register (sidr) is a register for inputting (receiving) serial data. n serial input data register (sidr) figure 14.4-6 "serial input data register (sidr)" shows the bit configuration of the serial input data register. figure 14.4-6 serial input data register (sidr) the sidr is a register for storing the received data. the serial data signal sent to the serial input pin (ui pin) is converted in the shift register and stored in this register. ? when the received data is set to this register successfully, the received data flag bit (rdrf) is set to "1." if the reception interrupt request is enabled, an interrupt occurs. when the received data is stored in this register in an interrupt or when checking the rdrf bit with the program, the rdrf flag is cleared by reading the description in this register. r rr r rr rr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 3 h address xxxxxxxx b initial value r : read only x : undefined
348 chapter 14 uart/sio 14.4.6 serial output data register (sodr) the serial output data register (sodr) is a register for outputting (transmitting) serial data. n serial output data register (sodr) figure 14.4-7 "serial output data register (sodr)" shows the bit configuration of the serial output data register. figure 14.4-7 serial output data register (sodr) when the data to be transmitted is written to this register after reading the ssd register in the transmission permitted state, the transmission data is transferred to the shift register for transmission, converted into serial data, and transmitted from the serial data output pin (uo pin). when the transmission data is written to the sodr register, the transmission data flag bit is set to "0." after the transmission data is transferred to the shift register for transmission, the transmission data flag bit is set to "1" so that the next transmission data can be written in the register. if the interrupt request is enabled at this time, an interrupt occurs. the next transmission data can be written by generating an interrupt or when the transmission data flag bit is set to "1." bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 3 h address xxxxxxxx b initial value w ww w ww w w r : write only x : undefined
349 14.5 uart/sio interrupt 14.5 uart/sio interrupt the uart/sio has three flags related to interrupts, the error flag bits (per, ove, fer), the received data flag bit (rdrf), and the transmission data flag bit (tdre), as well as the following two interrupt sources. ? when the received data is transferred from the shift register for reception to the serial input data register (sidr) ? when the transmission data is transferred from the serial output data register (sodr) to the shift register for transmission. n transmission interrupt when the output data is written to the sodr register, the data written to the sodr register is transferred to the shift register for internal transmission. when the register is ready to accept the next data, the tdre bit is set to "1." if the transmission interrupt is enabled (smc2: tie = 1), an interrupt request to the cpu (irq6) occurs. n reception interrupt after data is input up to the stop bit successfully, the rdrf bit is set to "1." if an overrun, parity, or error framing error has occurred, the bit of the corresponding error flag is set to "1." these bits are set when the stop bit is detected. if the reception interrupt is enabled (ssd: rie = 1), an interrupt request to the cpu (irq6) occurs. n register and vector table address related to interrupt of uart/sio for interrupt operation, see section 3.4.2 "interrupt processing". table 14.5-1 register and vector table address related to interrupt of uart/sio interrupt name interrupt level setting register vector table address register bit to be set upper lower irq6 ilr2 (007ch) l61 (bit 5) l60 (bit 4) ffee h ffef h
350 chapter 14 uart/sio 14.6 operation of the uart/sio this section describes the operation of the uart/sio. the uart/sio has ordinary serial communication functions (operation modes 0 and 1). n operation of uart/sio m operation modes the uart/sio has two operation modes: clock synchronous mode (sio) and clock asynchronous mode (uart). (see table 14.1-1 "operation mode of uart/sio".)
351 14.7 operation of the operation mode 0 14.7 operation of the operation mode 0 operation mode 0 operates in clock asynchronous mode. n explanation of operation mode 0 of uart/sio the serial clock is selected, with bits clk2 to clk0 in the smc1 register, from among three types of internal clocks, an external clock, and a baud rate generator output. when the external clock is selected, the clock must be entered. in clk asynchronous mode, the shift clock selected with bits clk2 to clk0 is divided by eight and data can be transferred in the range between -2% and +2% of the selected baud rate. the baud rate calculation expressions for the internal and external clocks and the baud rate generator are shown in the following. figure 14.7-1 baud rate calculation expression for internal and external clocks figure 14.7-2 baud rate calculation expression when the dedicated baud rate generator is used baud rate value clock selected with the bits clk2 to clk0 1 [bps] 8 64/f ch 16/f ch 8/f ch 4/f ch 1 [bps] baud rate value f ch : main clock oscillation frequency src register value (src) clock gear selection
352 chapter 14 uart/sio n transfer data format the uart/sio can only use the nrz (non return to zero) format data. figure 14.7-3 "transfer data format" shows the data format. in the following example, the stop bit length is two bits. as shown in figure 14.7-3 "transfer data format", data transfer always starts with the start bit ("l" level), followed by the data bit length specified as the lsb first, and ends with the stop bit ("h" level). in an idle state, it is at the "h" level. table 14.7-1 example of the asynchronous transfer rate with the baud rate generator (in 4/ fch clock gear) operating frequency 10 mhz 8 mhz 7.3728 mhz 4.9152 mhz instruction cycle 0.4 m m m m s0.5 m m m m s0.54 m m m m s 0.81 m m m m s baud rate values in parentheses indicate src register set values 78125(n=2) 62500(n=2) C 76800(n=1) 39062(n=4) 31250(n=4) 38400(n=3) 38400(n=2) 19531(n=8) 17857(n=7) 19200(n=6) 19200(n=4) 9765(n=16) 9615(n=13) 9600(n=12) 9600(n=8) 4882(n=32) 4807(n=26) 4800(n=24) 4800(n=16) 2403(n=65) 2403(n=52) 2400(n=48) 2400(n=32) 1201(n=130) 1201(n=104) 1200(n=96) 1200(n=64) C 600(n=208) 600(n=192) 600(n=128) CCC300(n=0)
353 14.7 operation of the operation mode 0 figure 14.7-3 transfer data format n receiving operation in clk asynchronous mode select the baud rate clock with bits clk2 to clk0 in the smc2 register. for the baud rate clock, see figure 14.7-1 "baud rate calculation expression for internal and external clocks" and figure 14.7-2 "baud rate calculation expression when the dedicated baud rate generator is used". in a receiving operation, reception is permitted when the rxe bit in the smc1 register is "1" and the receiving operation starts at the first falling edge of the input data (detection of the start bit). when the receiving operation is completed, the rdrf bit in the ssd register is set to "1" and the received data is loaded to the sidr register. if the rdrf bit is set to "1" when the rie bit is "1," a reception interrupt to the cpu is generated. if any of the three errors (per/ove/fer) is detected when reception is completed, the rdrf bit is not set to "1" and the received data is not loaded to the sidr register. therefore, the value in the sidr register is the previously received data. unless the rxe bit is set to "0," the receiving operation is continued whenever a start bit is detected even if an error flag is set. figure 14.7-4 receiving operation of clk asynchronous mode if "0" is written to the rxe bit of the smc2 register during a receiving operation, the receiving operation is prohibited after data reception is completed. st d0 d1 d2 d3 d4 d5 d6 sp sp 7-bit length no parity stop bits: 2 bits st d0 d1 d2 d3 d4 d5 d6 sp sp 7-bit length with parity stop bits: 2 bits p st d0 d1 d2 d3 d4 d5 d6 sp sp 8-bit length no parity stop bits: 2 bits d7 st d0 d1 d2 d3 d4 d5 d6 sp sp 8-bit length with parity stop bits: 2 bits d7 p st : start bit d0 to d7 : data bit p : parity bit sp : stop bit si st d0 d1 d2 d3 d4 d5 d6 sp sp d7 st d0 d1 d2 rxe load to sidr rdrf
354 chapter 14 uart/sio n reception error in clk asynchronous mode in clk asynchronous mode, three types of errors are detected. when a parity error, overrun error, or framing error is detected, the per, ove, or fer bit in the ssd register is set to "1," respectively. the detection of these errors are performed at the end of reception as shown in the following. when any of these errors is detected, rdrf is not set and the received data is not loaded to the sidr register. therefore, the value in the sidr register is the previously received data. by writing "0" to the rerc bit in the scm2 register, all of the three error flags are cleared. figure 14.7-5 reception error setting timing n detecting the start bit at receiving operation when the "l" level remains for four clocks with the selected serial clock (generator output, etc.) after the first falling edge of the input data, the uart/sio regards it as a start bit. after the start bit is detected, data is sampled at the rising edge of the fifth clock of the serial clock after the start bit is detected. figure 14.7-6 detecting a start bit si d5 d6 sp sp d7 error interrupt per ove fer 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 d0 serial clock si four clocks a start bit is detected. data is sampled. st : start bit d0 to d7: data bit
355 14.7 operation of the operation mode 0 n transmitting operation in clk asynchronous mode if transmission data is written to the sodr register when the txe bit in the smc2 register is "1," the tdre bit in the ssd register is cleared and a transmitting operation starts. when the data in the sodr register is loaded to the shifter and the output of transmission data starts, the tdre bit in the ssd register is set. if data is written to the sodr register when data is being transmitted (when the tdre bit is set to "1"), the tdre bit is cleared and data is transmitted continuously following the transmission of the specified bit length data. if "0" is written to the txe bit in the smc2 register during a transmitting operation, the transmitting operation is prohibited following the transmission of the specified bit length data when the sodr register is vacant (when the tdre bit is set to "1"). when there is data in the sodr register (when the tdre bit is set to "1"), the transmitting operation is prohibited after the data in the sodr register is transmitted. figure 14.7-7 transmission in clk asynchronous mode so st d0 d1 d2 d3 d4 d5 d6 sp sp d7 st d0 d1 d2 txe load to sodr tdre interrupt to the cpu interrupt to the cpu st : start bit d0 to d7: data bit sp : stop bit
356 chapter 14 uart/sio 14.8 operation of the operation mode 1 operation mode 1 operates in clock synchronous mode. n explanation of uart/sio operation mode in clk synchronous mode, the clock is selected, with bits clk2 to clk0 in the smc1 register, from among three types of internal clocks, an external clock, and a baud rate generator output. shift operation is performed with the selected clock as a shift clock. when the external clock is entered, set the scke bit to "0". when the internal clock or the output of the baud rate generator is output as a shift clock, set the scke bit to "1". the baud rate calculation expressions for the internal and external clocks and the baud rate generator are shown in the following figure 14.8-1 baud rate calculation expression for the internal and external clocks (operation mode 1) figure 14.8-2 baud rate calculation expression when the dedicated baud rate generator is used (operation mode 1) baud rate value clock selected with bits clk2 to clk0 1 [bps] baud rate value src register value (src) f ch : main clock oscillation frequency 64/f ch 16/f ch 8/f ch 4/f ch clock gear selection f ch [bps]
357 14.8 operation of the operation mode 1 n 8-bit receiving operation at operation mode 1 in reception in operation mode 1, use each register as shown in the following. figure 14.8-3 registers used during reception in operation mode 1 a receiving operation is permitted by setting the txe/rxe bits to "11" and started by writing to the sodr register. the receiving operation is performed in synch with the rising edge of the shift clock. when the reception of 8-bit data is completed, the data in the shifter is loaded to the sidr register and the rdrf flag is set to "1." when rie is "1" at this time, an interrupt request to the cpu is generated. if an overrun error is detected at the end of reception, data is not loaded to the sidr register. if "0" is written to the rxe bit during the receiving operation, the receiving operation is stopped after reception of the 8-bit data. in the serial operation stop state, maintain the input of the serial clock at the "h" level (irrespective of the value of the rxe bit). md tdp sbl bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 pen cl clk1 clk0 clk2 10 01 brge bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 txoe rie tie scke rerc rxe txe -- per ove fer rdrf tdre - 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smc 1 (serial mode control register 1) smc 2 (serial mode control register 2) ssd (serial status and data register) : used bit x : unused bit 1 : 1 is set 0 : 0 is set
358 chapter 14 uart/sio figure 14.8-4 8-bit data receiving operation in clk synchronous mode n continuous receiving operation in clk synchronous mode, not only an 8-bit data receiving operation but also a continuous receiving operation can be performed. in the continuous receiving operation, the tie bit in the smc2 register and the tdre bit in the ssd register are used in addition to the registers used in the 8-bit data receiving operation. the receiving operation is permitted by setting the txe/rxe bits to "11" and started by writing to the sodr register. the receiving operation is performed in synch with the rising edge of the shift clock. when a shift operation starts, the tdre bit is set to "1." when tie is "1" at this time, an interrupt to the cpu is generated. by writing to the sodr register before the shift operation of 8-bit data is completed, the next shift operation is permitted and the receiving operation is performed continuously after the reception of 8-bit data. when the reception of 8-bit data is completed, the data in the shifter is loaded to the sidr register and the rdrf flag is set to "1." when rie is "1" at this time, an interrupt request to the cpu is generated. if an overrun error is detected at the end of reception, data is not loaded to the sidr register and the description in the sidr register is the previously received data. by reading the sidr register, a reception interrupt (rdrf) is cleared. by writing "0" to the rxe bit, the receiving operation is stopped. if "0" is written to the rxe bit during the receiving operation, the receiving operation is stopped after 8-bit data is received. si d0 d1 d2 d3 d4 d5 d6 d7 sck load to sidr rdrf write to sodr interrupt to cpu
359 14.8 operation of the operation mode 1 figure 14.8-5 continuous receiving operation in clk synchronous mode n 8-bit transmitting operation at operation mode 1 in transmission in operation mode 1, use each register as shown in the following. si d0 d1 d2 d3 d4 d5 d6 d7 sck load to sidr rdrf write to sodr interrupt to cpu d0 d1 d2 d3 d4 d5 d6 d7 tdre read of sidr interrupt to cpu
360 chapter 14 uart/sio figure 14.8-6 registers during transmission in operation mode 1 a transmitting operation is permitted by setting the txe/rxe bits to "11" and started by writing data to the sodr register. when transmitting operation is started, the data written to the sodr register is loaded to the shifter and the shift operation is performed. when the data in the sodr register is loaded to the shifter, the tdre flag is set to "1." when tie is "1" at this time, an interrupt request to the cpu is generated. output of the serial data is permitted with txoe = "1" and is output in synch with the falling edge of the shift clock. if "0" is written to the txe bit during the transmitting operation, the operation is stopped after 8- bit data is transmitted. after the 8-bit data is transmitted, the rdrf bit is set to "1." if rie is "1" at this time, an interrupt request to the cpu is generated. data transmission starts with bit 0 and ends with bit 7. in the serial operation stop state, maintain the input of the serial clock at the "h" level (irrespective of the value of the txe bit). md tdp sbl bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 pen cl clk1 clk0 clk2 10 01 brge bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 txoe rie tie scke rerc rxe txe -- per ove fer rdrf tdre - 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smc1 (serial mode control register 1) smc2 (serial mode control register 2) ssd (serial status and data register) : used bit x : unused bit 1 : 1 is set 0 : 0 is set
361 14.8 operation of the operation mode 1 figure 14.8-7 8-bit transmitting operation in clk synchronous mode n continuous transmission at operation mode 1 in clk synchronous mode, not only 8-bit data transmission but also continuous transmission can be performed. the transmitting operation is performed by setting the txe/rxe bits to "11" and writing data to the sodr register. when transmission starts, the data written to the sodr register is loaded to the shifter and the shift operation is performed. when the data in the sodr register is loaded to the shifter, the tdre flag is set to "1." when tie is set to "1" at this time, an interrupt request to the cpu is generated. a continuous operation is performed by writing the next transmission data to the sodr register during the transmitting operation when the tdre bit is "1" (the sodr register is vacant). by writing data to the sodr register, the tdre bit is cleared. after 8-bit data is transmitted, the data written to the sodr register is loaded to the shifter and the transmitting operation is performed continuously. by writing "0" to the txe bit, the transmitting operation is stopped. if "0" is written to the txe bit during the transmitting operation, the transmitting operation is stopped after 8-bit data is transmitted when the sodr register is vacant (when the tdre bit is "1"). when there is data in the sodr register (when the tdre bit is "0"), the transmitting operation is stopped after the data in the sodr register is transmitted. when 8-bit data transmission is completed, the rdrf bit is set to "1." when rie is "1" at this time, an interrupt request to the cpu is generated. si d0 d1 d2 d3 d4 d5 d6 d7 sck rdrf write to sodr interrupt to cpu tdre interrupt to cpu
362 chapter 14 uart/sio figure 14.8-8 continuous receiving operation in clk synchronous mode si d0 d1 d2 d3 d4 d5 d6 d7 sck rdrf write to sodr interrupt to cpu tdre interrupt to cpu d0 d1 d2 d3
363 chapter 15 i 2 c this chapter describes the functions and operations of the i 2 c. 15.1 "overview of the i 2 c" 15.2 "configuration of the i 2 c" 15.3 "pins of the i 2 c" 15.4 "registers of the i 2 c" 15.5 "i 2 c interrupts" 15.6 "operation of the i 2 c" 15.7 "notes on using the i 2 c" 15.8 "operation of timeout detection function"
364 chapter 15 i 2 c 15.1 overview of the i 2 c the i 2 c is a simple bidirectional bus consisting of two wires that transfer data among devices. these two i 2 c bus interfaces allow internal devices requiring address data to connect to one another with a minimum number of circuits, making it possible to construct less expensive hardware using a fewer number of pcbs. the i 2 c interface that supports philips's i 2 c bus specification and intel's sm bus specification provides master/slave transmission and reception, arbitration lost detection, slave address/general call address detection, generation and detection of start/stop conditions, and buss error detection. n i 2 c functions the i 2 c interface is a simple structure bidirectional bus consisting of two wires: a serial data line (sda) and a serial clock line (scl). among the devices connected with these two wires, information is transmitted to one another. by recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. among these devices, the master/slave relation is established. the i 2 c interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400pf. it is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. a configuration example of the i 2 c interface is shown in figure 15.1-1 "i 2 c block diagram". the communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. multi-master means that multiple masters attempt to control the bus simultaneously without losing messages.
365 15.1 overview of the i 2 c figure 15.1-1 i 2 c block diagram sda scl microcontroller a lcd driver static ram/ e 2 prom gate array a/d converter microcontroller b
366 chapter 15 i 2 c 15.2 configuration of the i 2 c the i 2 c consists of the following 14 blocks. ? clock selector, clock divider, shift clock generator ? start/stop condition generator ? start/stop condition detector ? arbitration lost detector ? timeout detector ? slave address comparator ?i 2 c bus status register (ibsr) ?i 2 c bus control register (ibcr) ?i 2 c clock control register (iccr) ?i 2 c address register (iadr) ?i 2 c data register (idar) ?i 2 c timeout control register (itcr) ?i 2 c timeout status register (itsr) ?i 2 c timeout data register (itod) ?i 2 c timeout clock register (itoc) ?i 2 c slave timeout register (isto) ?i 2 c master timeout register (imto)
367 15.2 configuration of the i 2 c n i 2 c block diagram figure 15.2-1 i 2 c block diagram internal data bus scc beie mss ack gcaa inte int ber al rsc lrb trx aas gca fbt bb ibsr start/stop condition generator clock selector 1 clock selector 2 clock frequency divider 1 clock divider 2 shift clock generator error sync start master enables ack enables gc-ack bus busy repeat start last bit transmission/ reception slave arbitration lost detector sda line scl line first byte i c enable start/stop condition detector idar register iadr register slave address comparator iccr en cs2 cs1 cs0 ibcr ibcr ibsr irq9 end 8 5 peripheral clock shift clock edge general call dmbp timeout detector itcr itsr itod itoc isto imto cs4 cs3 678 16 32 64 128 256 512 4 2
368 chapter 15 i 2 c m clock selector, clock divider, shift clock generator this circuit selects and generates a shift clock of the i 2 c bus based on the internal clock. m start/stop condition generator when the bus is released (when the scl and sda lines are at a "h" level), transmitting a start condition causes the master to start communication. when the sda line is changed from "h" to "l" when scl = h, a start condition is generated. when a stop condition is generated, the master can stop communication. the stop condition is generated when the sda line is changed from "l" to "h" when scl = h. m start/stop condition detector this circuit detects the start/stop condition for data transfer. m arbitration lost detector this interface circuit supports the multi-master system. if two or more masters transmit data simultaneously, arbitration lost is generated. when logic level "1" is transmitted when the sda line is at level "l", this state is regarded as arbitration lost. at this time, ibsr:al is set to "1" and the master is changed into a slave. m slave address comparator after a start condition is transmitted, a slave address is transmitted. this address is seven-bit data, followed by a data direction bit (r/w) as bit 8. ack is returned only to the slave whose address matches the transmitted address. m timeout detector this circuit detects a timeout based on the value set in the itod, itoc, isto, and imto registers. m ibsr register the ibsr register indicates the status of the i 2 c interface. this register is read-only. m ibcr register the ibcr register is used to select the operating mode, enables/disables interrupts, enables/ disables acknowledge, and enables/disables general call acknowledge. m iccr register the iccr register is used to permit the operation of the i 2 c interface and select the shift clock frequency. m iadr register the iadr register is used to set the slave address. m idar register the idar register is used to hold the shift data transmitted/received. in transmission, the data written in this register is transferred to the bus from the msb in turn. m itcr register the itcr register is used to enable/disable the operation of the timeout detector and to control interrupts.
369 15.2 configuration of the i 2 c m itsr register the itsr register is used to check the detection state of the timeout detector. m itod register the itod register is used to set the count value for a i 2 c timeout in the data line. m itoc register the itoc register is used to set the count value for a i 2 c timeout in the clock line. m isto register the isto register is used to set the count value for a i 2 c slave timeout. m imto register the imto register is used to set the count value for a i 2 c master timeout. m i 2 c interface interrupt source irq9: an interrupt request is generated by the i 2 c interface when the bus error interrupt request bit is enabled (ibcr: beie = "1") and a bus error has occurred or when the transfer end interrupt enable bit is enabled (ibcr: inte = "1") and data transfer is completed. irqa: a timeout interrupt is generated if the set timeout is expired when the timeout detection function is enabled (itcr: ts0 to ts2 are other than "000").
370 chapter 15 i 2 c 15.3 pins of the i 2 c this section shows the pins related to the i 2 c and the block diagram of pins. n pins related to the i 2 c the pins related to the i 2 c include the clock i/o pin (p33/scl2/uck3) and the serial data i/o pin (p34/sda2/ui3). they can be switched by the bridge circuit selection register (brsr1 to 3), the operating port selection bit (smc2: txoe) of uart serial mode control register 2, and the i 2 c operation enable bit (iccr: en). p34/sda2/ui3 pin the p34/sda2/u13 pin serves as an n-ch open-drain i/o port (p34), a i 2 c data i/o pin (sda2), and a bridge circuit uart serial data input pin (ui3). p33/scl2/uck3 pin the p33/scl2/uck3 pin serves as an n-ch open-drain i/o port (p33), a i 2 c shift clock i/o pin (scl2), and a bridge circuit uart serial clock i/o pin (uck3).
371 15.3 pins of the i 2 c n block diagram of pins related to i 2 c figure 15.3-1 block diagram of pins related to i 2 c note: when the i 2 c function is used, p33/scl2 and p34/sda2 pins must be pulled up externally. pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus pin pdr read i 2 c output multi-address i 2 c output i 2 c input from bridge circuit from bridge circuit from bridge circuit from bridge circuit multi-address i 2 c input pin stop/watch mode stop/watch mode stop/watch mode output tr. uart input uart output (p33 only) p33/scl2 p34/sda2 spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
372 chapter 15 i 2 c 15.4 registers of the i 2 c this section shows the registers related to the i 2 c. n registers related to i 2 c figure 15.4-1 registers related to i 2 c 0 0 3 5 h address 00000000 b initial value address initial value address initial value address initial value address initial value address initial value ibsr (i 2 c bus status register) bb al rsc bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r gca fbt r r rr lrb trx aas r rr 0 0 3 7 h 0x0xxxxx b iccr (i 2 c clock control register) dmbp en - - -- bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w cs1 cs0 r/w r/w r/w r/w cs4 cs3 cs2 r/w r/w 0 0 3 8 h xxxxxxxx b iadr (i 2 c address register) a5 a6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w a1 a0 r/w r/w r/w a4 a3 a2 r/w r/w r/w 0 0 3 6 h 00000000 b ibcr (i 2 c bus control register) ber scc beie bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w inte int r/w r/w r/w r/w mss ack gcaa r/w r/w r/w 0 0 3 9 h xxxxxxxx b idar (i 2 c data register) d7 d5 d6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w d1 d0 r/w r/w r/w r/w d4 d3 d2 r/w r/w r/w 0 0 3 a h x0000000 b itcr (i 2 c timeout control register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w r/w r/w toe ts1 ts0 ext ts2 aac
373 15.4 registers of the i 2 c address initial value address initial value address initial value address initial value address initial value -- - - bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 e h xxxxxxxx b r/w r/w r/w r/w r/w r/w isto (i 2 c slave timeout register) r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 c h xxxxxxxx b r/w r/w r/w r/w r/w r/w itod (i 2 c timeout data register) r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 f h xxxxxxxx b r/w r/w r/w r/w r/w r/w imto (i 2 c master timeout register) r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 d h xxxxxxxx b r/w r/w r/w r/w r/w r/w itoc (i 2 c timeout clock register) r/w r/w 0 0 3 b h xxxx0000 b itsr (i 2 c timeout status register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w tcr str mtr tdr : read/write enabled : read only : undefined
374 chapter 15 i 2 c 15.4.1 i 2 c bus status register (ibsr) the ibsr register indicates the status of the interface. n i 2 c bus status register (ibsr) figure 15.4-2 i 2 c bus status register (ibsr) rr r r lrb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 5 h address 00000000 b initial value trx aas gca fbt r trx 0 1 reception mode transmission mode aas 0 1 addressing detection bit gca 0 1 in slave mode, the general call address (00h) is not received in slave mode, the general call address (00h) is received data transfer state bit general call address detection bit not addressed in slave mode addressed in slave mode fbt 0 the received data is a byte other than the first byte when data is received the received data is the first byte (address data) when data is received first byte detection bit r r r bb rsc al lrb 0 the acknowledge generated by the receiving end is detected at the ninth shift clock not acknowledged at the ninth shift clock acknowledge storage bit bb 0 1 stop condition is detected start condition is detected bus busy bit rsc 0 1 repeated start condition is not detected start condition is detected again when the bus is in use repeated start condition detection bit al 0 arbitration lost is not detected arbitration lost bit arbitration lost is generated while the master is transmitting data or "1" is written to the ibcr: mss bit when another system is using the bus 1 1 1 r/w : read only : initial value
375 15.4 registers of the i 2 c table 15.4-1 functions of each bit in i 2 c bus status register (ibsr) bit name function bit 7 bb: bus busy bit this bit indicates the state of the bus. this bit is cleared when a stop condition is detected and set when a start condition is detected. bit 6 rsc: repeated start condition detection bit this bit detects the repeated start condition. this bit is set when a start condition is detected and cleared in the following state. ? "0" is written to the ibcr: int bit ? the slave address does not match the set address ? a start condition is detected during bus stop ? a stop condition is detected bit 5 al: arbitration lost bit this bit detects arbitration lost. this bit is set in the following states. ? arbitration lost is detected when the master is transmitting data ? "1" is written to the ibcr: mss bit when another system is using the bus this bit is also cleared when "0" is written to the ibcr: int bit bit 4 lrb: acknowledge storage bit this bit stores the sda line value of the 9th clock when the data byte is transferred. ? cleared when an acknowledge bit is detected. (sda = l) ? set when an acknowledge bit is not detected. (sda = h) ? cleared with "0" when a start or stop condition is detected. bit 3 trx: data transfer state bit this bit indicates whether the data transfer is performed in the transmission mode or the reception mode. bit 2 aas: addressing detection bit this bit indicates addressing is performed in slave mode. this bit is set when addressing is performed in slave mode and cleared when a start or stop condition is detected. bit 1 gca: general call address detection bit this bit detects a general call address. if this bit is set to "1" in slave mode, the general call address (00h) is received. this bit is cleared when a start or stop condition is detected. bit 0 fbt: first byte detection bit this bit detects the first byte this bit is always set to "1" in the start condition. this bit is set to "1" when a start condition is detected and cleared when "0" is written to the ibcr: int bit or when the set address does not match its address in slave mode.
376 chapter 15 i 2 c 15.4.2 i 2 c bus control register (ibcr) the ibcr register is used to select the operating mode, enables/disables interrupts, enables/disables acknowledge, and enables/disables general call acknowledge. n i 2 c bus control register (ibcr) figure 15.4-3 i 2 c bus control register (ibcr) mss bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 6 h address 00000000 b initial value ack inte int gcaa r/w r/w r/w r/w r/w beie ber scc r/w r/w r/w transfer end interrupt request flag bit data transfer not completed clear read write read write read write int 0 1 gcaa 0 1 general call address acknowledge generation enable bit ack data acknowledge generation enable bit acknowledge is not generated acknowledge is generated 0 1 beie bus error interrupt request enable bit disables bus error interrupt request output enables bus error interrupt request output 0 1 one byte data transfer including acknowledge of the ninth clock completed no change inte interrupt request enable bit disables interrupt request output enables interrupt request output 0 1 acknowledge is not generated acknowledge is generated mss master/slave selection bit selects slave mode selects master mode 0 1 bus error interrupt request bit no bus error ber 0 1 an illegal start or stop condition is detected start condition generation bit always 0 no change no change scc 0 1 generates repeated start condition in master mode. clear r/w :read/write enabled :initial value
377 15.4 registers of the i 2 c table 15.4-2 functions of each bit in i 2 c bus control register (ibcr) bit name function bit 7 ber: bus error interrupt request flag bit this bit clears a bus error interrupt and detects a bus error. when a bus error is detected, "0" is written and the bus error interrupt is cleared. when "1" is written, there is no change and no effect on others. when an illegal start or stop condition is detected during data transfer, this bit is set to "1". for rmw instructions, "1" is always read. when this bit is set, the operation enable bit in the iccr register is cleared, the i 2 c enters the hold mode, and data transfer is terminated. bit 6 beie: bus error interrupt request enable bit this bit enables (beie = 1) or disables (beie = 0) the generation of a bus error interrupt request. when this bit is set and ber = 1, an interrupt request is sent to the cpu. bit 5 scc: start condition generation bit when this bit is set, a repeated start condition in master mode is generated. (scc = 1) no change when "0" is written. the read value of this bit is always "0". note: 1) do not write scc = 1 and mss = 0 simultaneously. 2) if "0" is written to mss when int = 0, "0" in the mss bit has a higher priority and a stop condition is generated. bit 4 mss: master/slave selection bit this bit selects the slave mode (mss = 0) or the master mode (mss = 1). when this bit is cleared to "0", a stop condition is generated and the master mode is switched to the slave mode after transfer is completed. when this bit is set to "1", the slave mode is switched to the master mode, a start condition is generated, and transfer is started. if arbitration lost is generated when the master is transmitting data, this bit is cleared and the master mode is switched to the slave mode. note: 1) do not write scc = 1 and mss = 0 simultaneously. 2) if "0" is written to mss when int = 0, "0" in the mss bit has a higher priority and a stop condition is generated. bit 3 ack: data acknowledge generation enable bit this bit enables (ack = 1) or disables (ack = 0) the output of the acknowledge bit in the 9th clock at data reception. bit 2 gcaa: general call address acknowledge generation enable bit this bit permits the generation of acknowledge when a general call address is received. when a general call address is received in slave mode when this bit is set to "1", output of acknowledge is permitted. even if a general call address is received when "0" is written to this bit, acknowledge is not output.
378 chapter 15 i 2 c note: when the interrupt request flag bit (ibcr: ber) is cleared, do not rewrite the interrupt request enable bit (ibcr: beie) simultaneously. only when the i 2 c enable bit (iccr: en) is set, values can be written to the ack, gcaa, and inte bits in the ibcr register. bit 1 inte: transfer end interrupt request enable bit this bit selects whether an interrupt at the end of transfer is enabled (inte = 1) or disabled (inte = 0). when this bit is set and int is set to "1", a transfer end interrupt request is sent to the cpu. bit 0 int: transfer end interrupt request flag bit with this bit, the data transfer end interrupt request flag can be cleared. in addition, it can be determined whether the interrupt is detected. when "0" is written, the transfer end interrupt request flag is cleared. when "1" is written, no change occurs. if any of the following four conditions is met when one byte transfer including the acknowledge bit is completed (including the acknowledge bit in the 9th clock), this bit is set to "1". ? bus master mode ? addressed slave ? a general call address is received ? arbitration lost is generated when this bit is set to "1", the scl line is kept at the "l" level. this bit is cleared when "0" is written to this bit. at this time, this macro releases the scl line and transfers the next byte. this bit is also cleared to "0" when a start or stop condition is generated in master mode. note: 1) if "1" is written to scc when int = 0, "1" in the scc bit has a higher priority and a start condition is generated. 2) if "0" is written to mss when int = 0, "0" in the mss bit has a higher priority and the stop condition is generated. for rmw instructions, "1" is always read. table 15.4-2 functions of each bit in i 2 c bus control register (ibcr) (continued) bit name function
379 15.4 registers of the i 2 c 15.4.3 i 2 c clock control register (iccr) the iccr register is used to permit the operation of the i 2 c and select the shift clock frequency. n i 2 c clock control register (iccr) figure 15.4-4 i 2 c clock control register (iccr) dmbp en cs4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 7 h address 0x0xxxxx b initial value r/w - en 0 1 disables i 2 c operation enables i 2 c operation cs3 cs1 cs0 cs2 r/w r/w r/w r/w r/w r/w i 2 c operation enable bit cs2 0 0 0 0 1 1 1 1 cs1 0 0 1 1 0 0 1 1 cs0 0 1 0 1 0 1 0 1 divider n 4 8 16 32 64 128 256 512 clock 2 selection bit dmbp 0 1 bypass prohibited bypass divider m divider m bypass bit cs4 0 0 1 1 cs3 0 1 0 1 divider m 5 6 7 8 clock 1 selection bit r/w x : read/write enabled : undefined : initial value
380 chapter 15 i 2 c table 15.4-3 functions of each bit in i 2 c clock control register (iccr) bit name function bit 7 dmbp: divider m bypass bit this bit is used to bypass the m divider for generating a shift clock frequency. when "0" is written, the value set in cs3 and cs4 becomes the value of the m divider. when "1" is written, the m divider is bypassed. this is equivalent to m = 1. in read cycle, the present set value can be read. when n = 0 (cs2 = cs1 = cs0 = 0), do not set this bit. bit 6 unused bit the read value is undefined. writing has no efect on operation. bit 5 en: multi-address i 2 c operation permission bit this bit permits the operation of the multi-address i 2 c interface (en = "1"). when the bit is "0", each bit of the mbsr and mbcr registers (excluding ber and beie bits) is cleared to "0". when the mbcr:ber bit is set, the bit is cleared. bit 4 bit 3 cs4, cs3: clock 1 selection bit this bit sets shift clock frequency. shift clock frequency fsck is determined by the following formula. bit 2 bit 1 bit 0 cs2, cs1, cs0: clock 2 selection bit where, f inst is an instruction cycle (the clock in the sycc selected by the scs bit). when dmbp is "0", m is selected by cs4 and cs3. when dmbp is "1," m is "1." n is selected by cs2, cs1, and cs0. (1) fsck = (m n +2) 2/t inst
381 15.4 registers of the i 2 c 15.4.4 i 2 c address register (iadr) the iadr register is used to set the slave address. n i 2 c address register (iadr) figure 15.4-5 i 2 c address register (iadr) in slave mode, the value in this register is compared with the slave address stored in iadr after the requested address is received. when they match, acknowledge is transmitted to the master as the 9th shift clock. a5 a6 - bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 8 h address xxxxxxxx b initial value r/w a1 a0 r/w r/w r/w a4 a3 a2 r/w iadr (i 2 c address register) r/w r/w r/w : read/write enabled x : undefined
382 chapter 15 i 2 c 15.4.5 i 2 c data register (idar) the idar register is used to set transmission data and to store received data. n i 2 c data register (idar) figure 15.4-6 i 2 c data register (idar) in master mode, the data written in the register is shifted to the sda line bit by bit from the msb bit. the write side in this register is made up of a double buffer. when the bus is in use (ibsr: bb = 1), written data is loaded to the eight-bit shift register when the transfer of the present byte is completed. the data in the shift register is shifted and output to the sda line bit by bit. the value written to this register has no effect on the present data transfer. also in slave mode, the same function can be used after the address is determined. when ibcr: int = 1 at data reception (ibsr: trx = 0), the received data can be read from this register. since the register for serial transfer is read directly in read cycle, the received data is effective only when ibcr: int = 1. d7 d5 d6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 9 h address xxxxxxxx b initial value r/w d1 d0 r/w r/w r/w r/w d4 d3 d2 r/w idar (i 2 c data register) r/w r/w r/w : read/write enabled x : undefined
383 15.4 registers of the i 2 c 15.4.6 i 2 c timeout control register (itcr) the itcr register is used to control the sm bus timeout detection. n i 2 c timeout control register (itcr) figure 15.4-7 "i 2 c timeout control register (itcr)" shows the bit configuration of the i 2 c timeout control register (itcr) figure 15.4-7 i 2 c timeout control register (itcr) toe bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 a h address x0000000 b initial value ext ts1 ts0 ts2 r/w r/w r/w r/w r/w ts2 0 0 0 0 1 1 1 1 ts1 0 0 1 1 0 0 1 1 ts0 0 1 0 1 0 1 0 1 timeout count clock selection bit (t) timeout detection is not allowed timeout detection clock 1 x (t inst/2) timeout detection clock 2 x (t inst/2) timeout detection clock 3 x (t inst/2) timeout detection clock 4 x (t inst/2) timeout detection clock 5 x (t inst/2) timeout detection clock 6 x (t inst/2) timeout detection clock 7 x (t inst/2) ext timeout detection extended bit timeout is detected only in master/slave mode timeout is detected also in other than master/slave mode toe 0 1 timeout interrupt bit disables interrupts enables interrupts 0 1 - aac - aac 0 1 ack control bit at addressing ack output is not allowed ack is output automatically r/w r/w x : read/write enabled : undefined : initial value
384 chapter 15 i 2 c table 15.4-4 functions of each bit in i 2 c timeout control register (itcr) bit name function bit 7 unused bit the read value is undefined. writing has no efect on operation. bit 6 aac: ack control bit at addressing this bit controls ack at address matching. when this bit is set to "1", ack control is performed automatically. (ack is returned automatically when the addresses match. when "0" is written to this bit, ack at addressing is not output. bit 5 test bit this bit is a test bit. write "1" when i 2 c is used. note: though the initial value of this bit is "0", write "1" to this bit when i 2 c is used. bit 4 toe: timeout interrupt enable bit this bit enables/disables timeout interrupts. when "1" is written to this bit, timeout interrupts are enabled and an interrupt request is sent to the cpu. when "0" is written to this bit, timeout interrupts are disabled. bit 3 ext: timeout detection extended bit this bit makes extended control for detecting a timeout. when "1" is written to this bit, the timeout detection function also operates in a mode other than master/slave mode. when "0" is written to this bit, the timeout detection function operates only in master/slave mode. note: this bit is effective only when timeout detection is enabled (itcr: ts0 to ts2 is other than "000".) bit 2 bit 1 bit 0 ts2, ts1, ts0: timeout count selection bits (t) these bits select the clock for detecting a timeout. when ts2 = 0, ts1 = 0, and ts0 = 0, the timeout detection function is disabled. with the clock selected in these bits [t x (t inst /2) x 10], the low period in the scl2 and sda2 lines is counted.
385 15.4 registers of the i 2 c 15.4.7 i 2 c timeout status register (itsr) the itsr register indicates the sm bus timeout detection status. n i 2 c timeout status register (itsr) 15.4-8 "i 2 c timeout status register (itsr)" shows the bit configuration of the i 2 c timeout status register (itsr). figure 15.4-8 i 2 c timeout status register (itsr) tdr str bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 b h address xxxx0000 b initial value mtr r/w r/w r/w r/w mtr master timeout interrupt request flag no master timeout a master timeout is detected 0 1 tcr 0 1 timeout clock interrupt request flag no timeout a timeout is detected str 0 1 slave timeout interrupt request flag no slave timeout a slave timeout is detected tcr - -- - tdr 0 1 timeout data interrupt request flag no timeout a timeout is detected r/w : read/write enabled x : undefined : initial value
386 chapter 15 i 2 c table 15.4-5 functions of each bit in i 2 c timeout status register (itsr) bit name function bit 7 bit 6 bit 5 bit 4 unused bits the read value is undefined. writing has no efect on operation. bit 3 tdr: timeout data interrupt request flag this bit detects a timeout of the data line. when timeout data is detected, this bit is set to "1". if timeout interrupts (itcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no significance. bit 2 tcr: timeout clock interrupt request flag this bit detects a timeout of the clock line. when a timeout clock is detected, this bit is set to "1". if timeout interrupts (itcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no significance. bit 1 mtr: master timeout interrupt request flag this bit detects a master timeout. when a master timeout is detected, this bit is set to "1". if master timeout interrupts (itcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no meaning. bit 0 str: slave timeout interrupt request flag this bit detects a slave timeout. when a slave timeout is detected, this bit is set to "1". if slave timeout interrupts (itcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no significance.
387 15.4 registers of the i 2 c 15.4.8 i 2 c timeout data register (itod) the itod register is used to detect an sm bus timeout (data line). n i 2 c timeout data register (itod) figure 15.4-9 "i 2 c timeout data register (itod)" shows the bit configuration of the i 2 c timeout data register (itod) figure 15.4-9 i 2 c timeout data register (itod) if the value written to this register plus one matches the counted value of the low time period of the sda2 line when the timeout detection function is enabled (itcr: ts0 to ts2 is other than "000"), the timeout data interrupt request flag (itsr: tdr) is set to "1". the low time period of the sda2 line is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 20. when the sda2 line is at a high level, the counter value is cleared to "0", and counting starts again when the sda2 line is at a low level. when the counter value matches "the value set in the timeout data register (itod) + 1", a timeout is detected and the timeout data interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 c h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
388 chapter 15 i 2 c 15.4.9 i 2 c timeout clock register (itoc) the itoc register is used to detect an sm bus timeout (clock line). n i 2 c timeout clock register (itoc) figure 15.4-10 "i 2 c timeout data register (itod)" shows the bit configuration of the i 2 c timeout clock register (itoc) figure 15.4-10 i 2 c timeout data register (itod) if the value written to this register plus one matches the counted value of the low time period of the scl2 line when the timeout detection function is enabled (itcr: ts0 to ts2 is other than "000"), the timeout clock interrupt request flag (itsr: tcr) is set to "1". the low time period of the scl2 line is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 20. when the scl2 line is at a high level, the counter value is cleared to "0" and counting starts again when the scl2 line is at a low level. when the counter value matches "the value set in the timeout clock register (itoc) + 1", a timeout is detected and the timeout clock interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 d h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
389 15.4 registers of the i 2 c 15.4.10 i 2 c master timeout register (imto) the imto register is used to detect an sm bus timeout. n i 2 c master timeout register (imto) figure 15.4-11 "i 2 c master timeout register (imto)" shows the bit configuration of the i 2 c master timeout register (imto) figure 15.4-11 i 2 c master timeout register (imto) when the value written to this register plus one matches the cumulative value of the low time period of the scl2 line counted from start to acknowledge (or from acknowledge to acknowledge or from acknowledge to stop) when the timeout detection function is enabled (itcr: ts0 to ts2 is other than "000"), the master timeout interrupt request flag (itsr: mtr) is set to "1". the low time period of the scl2 line is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 10. in master mode, the low time period cumulative value of the scl2 line is counted only when the scl2 line is at a low level and counting is stopped when the scl2 line is at a high level. at start, acknowledge or stop, or by exiting the master mode, the counter value is cleared to "0". when the counter value matches the value set in "the master timeout register (imto) + 1", a master timeout is detected and the master timeout interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 e h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
390 chapter 15 i 2 c 15.4.11 i 2 c slave timeout register (isto) the isto register is used to detect an sm bus timeout. n i 2 c slave timeout register (isto) figure 15.4-12 "i 2 c slave timeout register (isto)" shows the bit configuration of the i 2 c slave timeout register (isto) figure 15.4-12 i 2 c slave timeout register (isto) when the value written to this register plus one matches the cumulative value of the low time period of the scl2 line counted from start to stop when the timeout detection function is enabled (itcr: ts0 to ts2 is other than "000"), the slave timeout interrupt request flag (itsr: str) is set to "1". the low-time period of the scl2 line is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 20. in slave mode, the low-time period cumulative value of the scl2 line is counted only when the scl2 line is at a low level and counting is stopped when the scl2 line is at a high level. at start or stop or by exiting the slave mode, the counter value is cleared to "0". when the counter value matches "the value set in the slave timeout register (isto) + 1", a slave timeout is detected and the slave timeout interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 3 f h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
391 15.5 i 2 c interrupts 15.5 i 2 c interrupts the i 2 c interface may generate an interrupt request when the data transfer is completed, a bus error has occurred, or a timeout is detected. n interrupt at bus error when the following conditions are met, a bus error is assumed to have occurred and the i 2 c interface is stopped. 1. when a stop condition is detected in master mode. 2. when a start or stop condition is detected when the first byte is being transmitted and received. 3. when a start or stop condition is detected when data (excluding the first bit of start, stop, and data) is being transmitted and received. if the bus error interrupt request enable bit is enabled (ibcr: beie = 1) at this time, an interrupt request is output to the cpu. clear the interrupt request by writing "0" to the ber bit in the interrupt processing routine. if a bus error has occurred in spite of the beie bit value, the ber bit is set to "1". n interrupt at data transfer completion when data transfer is completed and the transfer end interrupt request enable bit is enabled (ibcr: inte = 1), an interrupt request (irq9) is output to the cpu. clear the interrupt request by writing "0" to the int bit in the interrupt processing routine. if data transfer is completed in spite of the inte bit value, the int bit is set to "1". n interrupt at timeout detection if the specified timeout time has expired when the timeout detection function is enabled (itcr: ts0 to ts2 is other than "000"), a timeout interrupt is generated (irqa). the timeout can be checked with each interrupt request flag of the i 2 c bus status register (itsr). when the timeout detection extended bit (itor: ext) is set, the bus is also monitored in a mode other than master/slave mode. n register and vector table address related to interrupt of i 2 c for interrupt operation, see section 3.4.2 "interrupt processing. table 15.5-1 register and vector table address related to interrupt of i 2 c interrupt name interrupt level setting register vector table address register bit to be set upper lower irq9 ilr3 (007dh) l91 (bit 3) l90 (bit 2) ffe8h ffe9h irqa ilr3 (007dh) la1 (bit 5) la0 (bit 4) ffe6h ffe7h
392 chapter 15 i 2 c 15.6 operation of the i 2 c the i 2 c interface is a serial data base of 8-bit data synchronized with the shift clock. n i 2 c system m operation mode the i 2 c bus system uses a serial data line (sda) and a serial clock line (scl) to transfer data. all connected devices require an open-drain or open collector output. the logic function is used by connecting a pull-up resistor. each device connected to the bus has a unique address and can be set by software. among the devices, simple master/slave relations are established and master devices function as master transmitters or master receivers. the i 2 c interface is a full-fledged multi-master bus equipped with collision detection and arbitration functions so that data destruction can be prevented even if two or more masters attempt to start data transfer simultaneously. n i 2 c protocol figure 15.6-1 "data transfer example" shows the format required for data transfer. figure 15.6-1 data transfer example after a start condition (s) is generated, a slave address is transmitted. this address is a seven- bit address followed by a data direction bit (r/w) as bit 8. data transfer is always ended with the master stop condition (p). it is also possible to address to another slave without generating a stop condition by generating a repeated start condition (sr). sda scl r/w lsb msb msb lsb start condition 7-bit address acknowledge bit 8-bit address no acknowledge stop condition
393 15.6 operation of the i 2 c n start condition when the master is not connected to the bus (the logic of scl and sda is "h") in states where the bus is released, the master generates a start condition. as indicated in figure 15.6-1 "data transfer example", a start condition is generated when the sda line is changed from "h" to "l" in states where scl is at the "h" level. at this time, new data transfer starts and master/slave operation starts. the two methods for generating a start condition are shown as follows. ? writing "1" to the ibcr: mss bit in states where the i 2 c bus is not used (ibcr: mss = 0, ibsr: bb = 0, ibcr: int = 0, ibsr: al = 0). thereafter, ibsr: bb is set to "1" to indicate bus busy. ? writing "1" to the ibcr: scc bit in interrupt states in bus master mode (ibcr: mss = 1, ibsr: bb = 1, ibcr: int = 1, ibsr: al = 0) and generates a repeated start condition. even if "1" is written to the ibcr: mss bit or "1" is written to the ibcr: scc bit under conditions other than the above conditions, it is ignored. if "1" is written to the ibcr: mss bit when another system is using the bus (in idle state), the ibsr: al bit is set to "1". n addressing in master mode, the bb and trx bits in the ibsr register are set to 1 after a start condition is generated and the contents of the idar register in the slave address are output from the msb in turn. this address data consists of 8-bits with a seven-bit slave address, followed by a r/w bit indicating the data transfer direction (bit 0 in idar). after the address data is transmitted, the master receives acknowledge from the slave. the sda line is set to "l" by the 9th clock and the master receives the acknowledge bit from the receiving end (see figure 15.6-1 "data transfer example"). at this time, the r/w bit (idar: bit 0) is reversed and stored in the ibsr: trx bit. in slave mode, the bb and trx bits in the ibsr register are set to "1" and "0", respectively, after a start condition is detected and data from the master is received by the idar register. after receiving the address data, the idar and iadr registers are compared. if the values match, ibsr: aas is set to "1" and acknowledge is transmitted to the master. thereafter, bit 0 of the received data (bit 0 in the idar register) is stored in the ibsr: trx bit. n data transfer after addressing of the slave is achieved, data can be transmitted and received in byte units in the direction determined by the r/w bit sent by the master. each byte output to the sda line is fixed to 8-bits. as shown in figure 15.6-1 "data transfer example", the receiving device transmits acknowledge to the transmitting device by stabilizing the sda line to the "l" level when the acknowledge clock pulse is "h". with the msb at the head, each bit of data is transmitted in one clock pulse. each time a byte is transferred, acknowledge must be transmitted and received. therefore, 9 clock pulses are required to transfer one complete data byte. n acknowledge acknowledge is transmitted from the receiving end for the 9th clock of data byte transfer from the transmitting end. when data is received, the acknowledge bit can be enabled (ibcr: ack = 1) or disabled (ibcr: ack = 0) with the ibcr: ack bit. when transmitting data, acknowledge from the receiving end is stored in the ibsr: lrb bit.
394 chapter 15 i 2 c n stop condition by generating a stop condition, the master can release the bus to terminate communication. a stop condition can be generated by changing the sda line from "l" to "h" when the scl line is at the "h" level. it is a signal to notify the bus connection device of the end of communication (bus free) in master mode. the master can generate start conditions continuously without generating a stop condition. this is called the repeated start condition. in bus master mode, a stop condition is generated by writing "0" to the ibcr: mss bit in the interrupt state (ibcr: mss = 1, ibsr: bb = 1, ibcr: int = 1, ibsr: al = 0) and the master mode is switched to the slave mode.. even if "0" is written to the ibcr: mss bit in other the above, it is ignored. n arbitration this interface circuit is a full-fledged multi-master bus that can connect two or more masters. if a master transfers data and another master transfers data simultaneously, an arbitration is generated. an arbitration occurs in the sda line when the scl line is at the "h" level. the master recognizes the occurrence of an arbitration lost when its transmission data is "1" and data on the sda line is at the "l" level, and then it sets data output to off and sets the ibsr: al bit to "1". when the ibsr: al is set to "1", "0" is written to ibcr: mss and ibsr: trx. as a result, the trx is cleared and the master mode is switched to the slave reception mode.
395 15.7 notes on using the i 2 c 15.7 notes on using the i 2 c this section describes precautions to take when using the i 2 c interface. n precaution in setting the i 2 c interface register before writing to the bus control register (ibcr), the i 2 c interface must be enabled (iccr: en). when the master slave selection bit (ibcr: mss) is set, transfer starts. n precaution in setting the shift clock frequency to calculate the shift clock frequency using the f sck expression (1) in table 15.4-3 "functions of each bit in i 2 c clock control register (iccr)", it is necessary to know the values of m, n, and dmbp. when n is 4 (iccr: cs2 = cs1 = cs0 = 0), "dmbp = 1" cannot be selected. other combinations do not present a problem. n precaution on the priority at simultaneous writing ? contention of the next byte transfer and stop condition when "0" is written to ibcr: mss in states where ibcr: int is cleared, the mss bit has a higher priority and a stop condition is generated. ? contention of the next byte transfer and start condition when "1" is written to ibcr: scc in states where ibcr: int is cleared, the scc bit has a higher priority and a start condition is generated. n precaution on setting with software do not select the repeated start condition (ibcr: en = 0) and the slave mode (ibcr: mss = 0) at the same time. in states where the interrupt request flag bits (ber and int in the ibcr register) are set to "1" and the interrupt request enable bits are enabled (beie and inte in the ibcr register are set to "1"), recovery from the interrupt processing cannot be performed. clear the ber and int bits in the ibcr register. when the i 2 c operation is not permitted (iccr: en = 0), all bits of the bus status register ibsr and the bus control register ibcr (excluding the bus error ber bit and the bus error enable beie bit) are cleared.
396 chapter 15 i 2 c 15.8 operation of the timeout detection function this section describes the operation of the timeout detection function when it is used as the sm bus. n data timeout when the "l" period of the sda2 line exceeds 25 ms, this state is defined as a data timeout. the low time period is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 20. when the counter value matches "the value set in the timeout data register (itod) + 1", a timeout is detected and the timeout data interrupt request flag (itsr: tdr) is set. figure 15.8-1 data timeout n clock timeout when the "l" period of the scl2 line exceeds 25 ms, this state is defined as a clock timeout. the low-time period is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 20. when the counter value matches "the value set in the timeout clock register (itoc) + 1", a timeout is detected and the timeout clock interrupt request flag (itsr: tcr) is set. figure 15.8-2 clock timeout sda2 data timeout 25 ms or more scl2 clock timeout 25 ms or more
397 15.8 operation of the timeout detection function n master timeout when the cumulative "l" period of the scl2 line between one byte data (start to ack, ack to ack, ack to stop) exceeds 10 ms in master mode, this state is defined as a master timeout. the low-time period is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 10. when the counter value matches "the value set in the master timeout register (imto) + 1", a master timeout is detected and the master timeout interrupt request flag (itsr: mtr) is set. figure 15.8-3 master timeout scl2 master timeout 10 ms or more start ack
398 chapter 15 i 2 c n slave timeout when the cumulative "l" period in the scl2 line between start and stop exceeds 10 ms in slave mode, this state is defined as a slave timeout. the low-time period is counted with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 20. when the counter value matches "the value set in the slave timeout register (isto) + 1", a slave timeout is detected and the slave timeout interrupt request flag (itsr: str) is set. figure 15.8-4 slave timeout scl2 slave timeout 25 ms or more start stop
399 15.8 operation of the timeout detection function n timeout clock supply block figure 15.8-5 "timeout clock supply block" shows the clock supply block of timeout. figure 15.8-5 timeout clock supply block n errors timeout detection is performed with the clock selected with the timeout count clock detection bits (itcr: ts0 to ts2) (t) divided by 10. therefore, the following errors occur in the detection of an "l" width when, for example, t = 0.5 m s. ? detects an "l" width of 5 to 5.5 m s or more in duration. (the sampling cycle is 0.5 m s) ? when the count is stopped (when low width detection is completed), an error of up to -5.5 m s in duration occurs. (in a cumulative count, errors are also accumulated.) the counter for detecting a timeout is incremented with an l width or cumulative l width of 100 m s or more (50 m s or more for a master timeout). ts0,1,2 scl2 line scl2 low detection clr clr h detection 1st byte detection start detection stop detection counter clr itoc comp counter clr imto comp counter clr isto comp clr clr sda2 line sda2 low detection low width detection low width detection divide-by-10 divide-by-10 divide-by-10 divide-by-20 divide-by-20 divide-by-20 clr t inst 2 t= clr h detection counter data timeout detection clock timeout detection master timeout detection slave timeout detection clr itod comp
400 chapter 15 i 2 c
401 chapter 16 multi-address i 2 c this chapter describes the functions and operations of the multi-address i 2 c. 16.1 "overview of the multi-address i 2 c" 16.2 "configuration of the multi-address i 2 c" 16.3 "pins of the multi-address i 2 c" 16.4 "registers of the multi-address i 2 c" 16.5 "multi-address i 2 c interrupts" 16.6 "operation of the multi-address i 2 c" 16.7 "notes on using the multi-address i 2 c" 16.8 "operation of the timeout detection function"
402 chapter 16 multi-address i 2 c 16.1 overview of the multi-address i 2 c the multi-address i 2 c is a simple bidirectional bus consisting of two wires that transfer data among devices. these two multi-address i 2 c bus interfaces allow internal devices requiring address data to connect to one another with a minimum number of circuits, making it possible to construct less expensive hardware using a fewer number of pcbs. the multi-address i 2 c interface that supports philips's multi-address i 2 c bus specification and intel's sm bus specification provides master/slave transmission and reception, arbitration lost detection, slave address/general call address detection, generation and detection of start/stop conditions, and buss error detection. n multi-address i 2 c functions the multi-address i 2 c interface is a simple structure bidirectional bus consisting of two wires: a serial data line (sda) and a serial clock line (scl). among the devices connected with these two wires, information is transmitted to one another. by recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. among these devices, the master/slave relation is established. the multi-address i 2 c interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400pf. it is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. this macro provides six addresses to implement the multi-address function. a configuration example of the multi-address i 2 c interface is shown in figure 16.1-1 "multi- address i 2 c block diagram". the communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. multi-master means that multiple masters attempt to control the bus simultaneously without losing messages.
403 16.1 overview of the multi-address i 2 c figure 16.1-1 multi-address i 2 c block diagram sda scl microcontroller a lcd driver static ram/ e 2 prom gate array a/d converter microcontroller b
404 chapter 16 multi-address i 2 c 16.2 configuration of the multi-address i 2 c the multi-address i 2 c consists of the following 14 blocks. ? clock selector, clock divider, shift clock generator ? start/stop condition generator ? start/stop condition detection ? arbitration lost detection ? timeout detection circuit ? slave address comparison circuit ? multi-address i 2 c bus status register (mbsr) ? multi-address i 2 c bus control register (mbcr) ? multi-address i 2 c clock control register (mccr) ? multi-address i 2 c address registers (madr1 to 6) ? multi-address i 2 c data register (mdar) ? multi-address i 2 c timeout control register (mtcr) ? multi-address i 2 c timeout status register (mtsr) ? multi-address i 2 c timeout data register (mtod) ? multi-address i 2 c timeout clock register (mtoc) ? multi-address i 2 c slave timeout register (msto) ? multi-address i 2 c master timeout register (mmto)
405 16.2 configuration of the multi-address i 2 c n multi-address i 2 c block diagram figure 16.2-1 multi-address i 2 c block diagram internal data bus scc beie mss ack gcaa inte int ber al rsc lrb trx aas gca fbt bb mbsr start/stop condition generator clock selector 1 clock selector 2 clock divider 1 clock divider 2 shift clock generator error sync start master enables ack enables gc-ack bus busy repeat start last bit transmission/ reception slave arbitration lost detector sda line scl line first byte i c enable start/stop condition detector mdar register madr register slave address comparator mccr en cs2 cs1 cs0 mbcr mbcr mbsr irqb end 8 5 peripheral clock shift clock edge general call dmbp timeout detector mtcr mtsr mtod mtoc msto mmto cs4 cs3 678 16 32 64 128 256 512 4 2
406 chapter 16 multi-address i 2 c m clock selector, clock divider, shift clock generator this circuit selects and generates shift clock for the multi-address i 2 c bus based on the internal clock. m start/stop condition generator when the bus is released (when the scl and sda lines are at a "h" level), transmitting a start condition causes the master to start communication . when the sda line is changed from "h" to "l" when scl = h, a start condition is generated. when a stop condition is generated, the master can stop communication. the stop condition is generated when the sda line is changed from "l" to "h" when scl = h. m start/stop condition detector this circuit detects the start/stop condition for data transfer. m arbitration lost detector this interface circuit supports the multi-master system. if two or more masters transmit data simultaneously, arbitration lost is generated. when logic level "1" is transmitted when the sda line is at level "l", this state is regarded as arbitration lost. at this time, mbsr: al is set to "1" and the master is changed into a slave. m slave address comparator after a start condition is transmitted, a slave address is transmitted. this address is seven-bit data, followed by a data direction bit (r/w) as bit 8. ack is returned only to the slave whose address matches the transmitted address. m timeout detector this circuit detects a timeout, based on the value set in the mtod, mtoc, msto, and mmto registers. m mbsr register the mbsr register indicates the status of the multi-address i 2 c interface. this register is read- only. m mbcr register the mbcr register is used to select the operating mode, enables/disables interrupts, enables/ disables acknowledge, and enables/disables general call acknowledge. m mccr register the mccr register is used to permit the operation of the multi-address i 2 c interface and select the shift clock frequency. m madr1 to 6 registers the madr1 to 6 registers is used to set the slave address. m mdar register the mdar register stores shift data that is transmitted/received. for transmission, data written in this register is transmitted to the bus, starting from msb. if this register is read during reception, "ff" is obtained.
407 16.2 configuration of the multi-address i 2 c m mtcr register this mtcr egister is used to enable/disable the operation of the timeout detector and to control interrupts. m mtsr register this mtsr register is used to check the detection state of the timeout detector. m mtod register the mtod register is used to set the count value for a multi-address i 2 c timeout in the data line. m mtoc register the mtoc register is used to set the count value for a multi-address i 2 c timeout in the clock line. m msto register the msto register is used to set the count value for a multi-address i 2 c slave timeout. m mmto register the msto register is used to set the count value for a multi-address i 2 c master timeout. m multi-address i 2 c interface interrupt source irqb: an interrupt request is generated by the multi-address i 2 c interface when the bus error interrupt request bit is enabled (mbcr: beie = "1") and a bus error has occurred or when the transfer end interrupt enable bit is enabled (mbcr: inte = "1") and data transfer is completed. irqc: a timeout interrupt is generated if the set timeout is expired when the timeout detection function is enabled (mtcr: ts0 to ts2 are other than "000").
408 chapter 16 multi-address i 2 c 16.3 pins of the multi-address i 2 c the pins related to the multi-address i 2 c and a pins block diagram is shown below. n pins related to the multi-address i 2 c the pins related to the multi-address i 2 c include the clock input/output pin (p30/scl1), serial data input/output pin (p31/sda1), and alert output pin (p32/alert). these pins are switched by the multi-address i 2 c operation enable bit (mccr:en) and multi-address i 2 c alert register. p31/sda1 pin: the p31/sda pin serves as an n-ch open-drain output port (p31) and a multi-address i 2 c data input/output pin (sda1). p30/scl1 pin: the p30/scl1 pin serves as an n-ch open-drain output port (p30) and a multi-address i 2 c shift clock input/output pin (scl1). p32/alert pin: the p32/alert pin serves as an n-ch open-drain output port (p32) and an alert output pin.
409 16.3 pins of the multi-address i 2 c n block diagram of pins related to multi-address i 2 c figure 16.3-1 block diagram of pins related to multi-address i 2 c note: when the multi-address i 2 c function is used, p30/scl1, p31/sda1, and p32/alert pins must be pulled up externally. pdr write pdr write output latch output latch stop /watch mode (spl=1) stop /watch mode (spl=1) pdr (port data register) pdr (port data register) internal data bus internal data bus pin resource input output tr. output tr. pdr read pdr read from the bridge circuit pin pin stop /watch mode stop /watch mode stop/watch mode p30/scl1 p31/sda1 from multi-address i 2 c permission bit from multi-address i 2 c output from the malr:aen bit of the multi-address i 2 c alert output spl: pin state designate bit of the standby control register (stbc) spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions) pdr read (for bit manipulation instructions)
410 chapter 16 multi-address i 2 c 16.4 registers of the multi-address i 2 c this section shows the registers related to the multi-address i 2 c. n registers related to multi-address i 2 c figure 16.4-1 registers related to multi-address i 2 c 0 0 4 0 h address 00000000 b initial value mbsr (multi-address i 2 c bus status register) bb al rsc bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r gca fbt rrrr lrb trx aas r rr 0 0 4 2 h address 0x0xxxxx b initial value mccr (multi-address i 2 c clock control register) dmbp en bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w cs1 cs0 r/w r/w r/w r/w cs4 cs3 cs2 r/w r/w address xxxxxxxx b initial value madr 1 to 6 (multi-address i 2 c address register 1 to 6) a5 a6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w a1 a0 r/w r/w r/w a4 a3 a2 r/w r/w r/w 0 0 4 1 h address 00000000 b initial value mbcr (multi-address i 2 c bus control register) ber scc beie bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w inte int r/w r/w r/w r/w mss ack gcaa r/w r/w r/w 0 0 4 9 h address xxxxxxxx b initial value mtcr (multi-address i 2 c timeout control register) - - - d5 d6 d7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w d1 d0 r/w r/w r/w r/w d4 d3 d2 r/w r/w r/w mdar (multi-address i 2 c data register) 0 0 4 a h address x0000000 b initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w r/w r/w r/w toe ts1 ts0 ext ts2 aac
411 16.4 registers of the multi-address i 2 c - - - - 0 0 4 e h address xxxxxxxx b initial value msto (multi-address i 2 c slave timeout register) 0 0 4 c h address xxxxxxxx b initial value mtod (multi-address i 2 c timeout data register) 0 0 4 f h address xxxxxxxx b initial value mmto (multi-address i 2 c master timeout register) 0 0 4 b h address xxxx0000 b initial value mtsr (multi-address i 2 c timeout status register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w tcr str mtr tdr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 4 d h address xxxxxxxx b initial value mtoc (multi-address i 2 c timeout clock register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w r/w r/w r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w r/w r/w r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 5 0 h address xxxx0000 b initial value malr (multi-address i 2 c alart register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w r/w arf aen ar0 arae r/w r/w -- - - r/w : read/write enabled r : read only x : undefined
412 chapter 16 multi-address i 2 c 16.4.1 multi-address i 2 c bus status register (mbsr) the mbsr register indicates the status of the interface. n multi-address i 2 c bus status register (mbsr) figure 16.4-2 multi-address i 2 c bus status register (mbsr) rr r r lrb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 0 h address 00000000 b initial value trx aas gca fbt r trx 0 1 reception mode transmission mode aas 0 1 addressing detection bit gca 0 1 in slave mode, the general call address (00h) is not received in slave mode, the general call address (00h) is received data transfer state bit general call address detection bit not addressed in slave mode addressed in slave mode fbt 0 the received data is a byte other than the first byte when data is received the received data is the first byte (address data) when data is received first byte detection bit r r r bb rsc al lrb 0 the acknowledge generated by the receiving end is detected at the ninth shift clock not acknowledged at the ninth shift clock acknowledge storage bit bb 0 1 stop condition is detected start condition is detected bus busy bit rsc 0 1 repeated start condition is not detected start condition is detected again when the bus is in use repeated start condition detection bit al 0 arbitration lost is not detected arbitration lost bit arbitration lost is generated while the master is transmitting data or "1" is written to the mbcr: mss bit when another system is using the bus 1 1 1 r/w : read only : initial value
413 16.4 registers of the multi-address i 2 c table 16.4-1 function of each bit in multi-address i 2 c bus status register (mbsr) bit name function bit 7 bb: bus busy bit this bit indicates the status of the bus. this bit is cleared when a stop condition is detected and set when a start condition or timeout is detected. bit 6 rsc: repeated start condition detection bit this bit detects the repeated start condition. this bit is set when a start condition is detected and cleared in the following state. ? "0" is written to the mbcr: int bit, ? the slave address does not match the set address ? a start condition is detected during bus stop ? a stop condition is detected bit 5 al: arbitration lost bit this bit detects arbitration lost. this bit is set in the following states. ? arbitration lost is detected when the master is transmitting data ? "1" is written to the mbcr: mss bit when another system is using the bus this bit is also cleared when "0" is written to the mbcr: int bit bit 4 lrb: acknowledge storage bit this bit stores the sda line value of the 9th clock when the data byte is transferred. ? cleared when an acknowledge bit is detected. (sda = l) ? set when an acknowledge bit is not detected. (sda = h) ? cleared with "0" when a start or stop condition is detected. bit 3 trx: data transfer state bit this bit indicates whether the data transfer is performed in the transmission mode or the reception mode. bit 2 aas: addressing detection bit this bit indicates addressing is performed in slave mode. this bit is set when addressing is performed in slave mode and cleared when a start or stop condition is detected. bit 1 gca: general call address detection bit this bit detects a general call address. if this bit is set to "1" in slave mode, the general call address (00h) is received. this bit is cleared when a start or stop condition is detected. bit 0 fbt: first byte detection bit this bit detects the first byte this bit is always set to "1" in the start condition. this bit is set to "1" when a start condition is detected and cleared when "0" is written to the mbcr: int bit or when the set address does not match its address in slave mode.
414 chapter 16 multi-address i 2 c 16.4.2 multi-address i 2 c bus control register (mbcr) the mbcr register is used to select the operating mode, enables/disables interrupts, enables/disables acknowledge, and enables/disables general call acknowledge. n multi-address i 2 c bus control register (mbcr) figure 16.4-3 multi-address i 2 c bus controller register (mbcr) mss bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 1 h address 00000000 b initial value ack inte int gcaa r/w r/w r/w r/w r/w beie ber scc r/w r/w r/w transfer end interrupt request flag bit data transfer not completed clear read write read write read write int 0 1 gcaa 0 1 general call address acknowledge generation enable bit ack data acknowledge generation enable bit acknowledge is not generated acknowledge is generated 0 1 beie bus error interrupt request enable bit disables bus error interrupt request output enables bus error interrupt request output 0 1 one byte data transfer including acknowledge of the ninth clock completed no change inte interrupt request enable bit disables interrupt request output enables interrupt request output 0 1 acknowledge is not generated acknowledge is generated mss master/slave selection bit selects slave mode selects master mode 0 1 bus error interrupt request bit no bus error ber 0 1 an illegal start or stop condition is detected start condition generation bit always 0 no change no change scc 0 1 generates repeated start condition in master mode. clear r/w : read/write enabled : initial value
415 16.4 registers of the multi-address i 2 c table 16.4-2 function of each bit in multi-address i 2 c bus controller register (mbcr) bit name function bit 7 ber: bus error interrupt request flag bit this bit clears a bus error interrupt and detects a bus error. when a bus error is detected, "0" is written and the bus error interrupt is cleared. when "1" is written, there is no change and no effect on others. when an illegal start or stop condition is detected during data transfer, this bit is set to "1". for rmw instructions, "1" is always read. when this bit is set, the operation enable bit in the mccr register is cleared, the multi-address i 2 c enters the hold mode, and data transfer is terminated. bit 6 beie: bus error interrupt request enable bit this bit enables (beie = 1) or disables (beie = 0) the generation of a bus error interrupt request. when this bit is set and ber = 1, an interrupt request is sent to the cpu. bit 5 scc: start condition generation bit when this bit is set, a repeated start condition in master mode is generated. (scc = 1) no change when "0" is written. the read value of this bit is always "0." note: 1) do not write scc = 1 and mss = 0 simultaneously. 2) if "0" is written to mss when int = 0, "0" in the mss bit has a higher priority and a stop condition is generated. bit 4 mss: master/slave selection bit this bit selects the slave mode (mss = 0) or the master mode (mss = 1). when this bit is cleared to "0," a stop condition is generated and the master mode is switched to the slave mode after transfer is completed. when this bit is set to "1," the slave mode is switched to the master mode, a start condition is generated, and transfer is started. if arbitration lost is generated when the master is transmitting data, this bit is cleared and the master mode is switched to the slave mode. note: 1) do not write scc = 1 and mss = 0 simultaneously. 2) if "0" is written to mss when int = 0, "0" in the mss bit has a higher priority and a stop condition is generated. bit 3 ack: data acknowledge generation enable bit this bit enables (ack = 1) or disables (ack = 0) the output of the acknowledge bit in the 9th clock at data reception. bit 2 gcaa: general call address acknowledge generation enable bit this bit permits the generation of acknowledge when a general call address is received. when a general call address is received in slave mode when this bit is set to "1," output of acknowledge is permitted. even if a general call address is received when "0" is written to this bit, acknowledge is not output.
416 chapter 16 multi-address i 2 c note: when the interrupt request flag bit (mbcr: ber) is cleared, do not rewrite the interrupt request enable bit (mbcr: beie) simultaneously. only when the multi-address i 2 c enable bit (mccr: en) is set, values can be written to the ack, gcaa, and inte bits in the mbcr register. bit 1 inte: transfer end interrupt request enable bit this bit selects whether an interrupt at the end of transfer is enabled (inte = 1) or disabled (inte = 0). when this bit is set and int is set to "1," a transfer end interrupt request is sent to the cpu. bit 0 int: transfer end interrupt request flag bit with this bit, the data transfer end interrupt request flag can be cleared. in addition, it can be determined whether the interrupt is detected. when "0" is written, the transfer end interrupt request flag is cleared. when "1" is written, no change occurs. if any of the following four conditions is met when one byte transfer including the acknowledge bit is completed (including the acknowledge bit in the 9th clock), this bit is set to "1." ? bus master mode ? addressed slave ? a general call address is received ? arbitration lost is generated when this bit is set to "1," the scl line is kept at the "l" level. this bit is cleared when "0" is written to this bit. at this time, this macro releases the scl line and transfers the next byte. this bit is also cleared to "0" when a start or stop condition is generated in master mode. note: 1) if "1" is written to scc when int = 0, "1" in the scc bit has a higher priority and a start condition is generated. 2) if "0" is written to mss when int = 0, "0" in the mss bit has a higher priority and the stop condition is generated. for rmw instructions, "1" is always read. table 16.4-2 function of each bit in multi-address i 2 c bus controller register (mbcr) (continued) bit name function
417 16.4 registers of the multi-address i 2 c 16.4.3 multi-address i 2 c clock control register (mccr) the multi-address i 2 c clock control register is used to enable the operation of multi- address i 2 c and to select shift clock frequency. n multi-address i 2 c clock control register (mccr) figure 16.4-4 multi-address i 2 c clock control register (mccr) dmbp en cs4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 2 h address 0x0xxxxx b initial value r/w - en 0 1 disables multi-address i 2 c operation enables multi-address i 2 c operation cs3 cs1 cs0 cs2 r/w r/w r/w r/w r/w r/w multi-address i 2 c operation enable bit cs2 0 0 0 0 1 1 1 1 cs1 0 0 1 1 0 0 1 1 cs0 0 1 0 1 0 1 0 1 divider n 4 8 16 32 64 128 256 512 clock 2 selection bit dmbp 0 1 bypass prohibited bypass divider m divider m bypass bit cs4 0 0 1 1 cs3 0 1 0 1 divider m 5 6 7 8 clock 1 selection bit r/w x : read/write enabled : undefined : initial value
418 chapter 16 multi-address i 2 c table 16.4-3 function of each bit in multi-address i 2 c clock control register (mccr) bit name function bit 7 dmbp: divider m bypass bit this bit is used to bypass the m divider for generating a shift clock frequency. when "0" is written, the value set in cs3 and cs4 becomes the value of the m divider. when "1" is written, the m divider is bypassed. this is equivalent to m = 1. in read cycle, the present set value can be read. when n = 0 (cs2 = cs1 = cs0 = 0), do not set this bit. bit 6 unused bit the read value is undefined. writing has no efect on operation. bit 5 en: multi-address i 2 c operation permission bit this bit permits the operation of the multi-address i 2 c interface (en = "1"). when the bit is "0", each bit of the mbsr and mbcr registers (excluding ber and beie bits) is cleared to "0". when the mbcr:ber bit is set, the bit is cleared. bit 4 bit 3 cs4, cs3: clock 1 selection bit this bit sets shift clock frequency. shift clock frequency fsck is determined by the following formula. bit 2 bit 1 bit 0 cs2, cs1, cs0: clock 2 selection bit where, f inst is an instruction cycle (the clock in the sycc selected by the scs bit). when dmbp is "0", m is selected by cs4 and cs3. when dmbp is "1," m is "1." n is selected by cs2, cs1, and cs0. (1) fsck = 2/t (m n +2) inst
419 16.4 registers of the multi-address i 2 c 16.4.4 multi-address i 2 c address registers (madr1 to 6) the madr1 to 6 registers are used to set slave addresses. n multi-address i 2 c address registers (madr1 to 6) figure 16.4-5 multi-address i 2 c address registers (madr1 to 6) in slave mode, the value in this register is compared with the slave address stored in madr1 to 6 after the requested address is received. when they match, acknowledge is transmitted to the master as the 9th shift clock. a5 a6 - bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 3 h 0 0 4 8 h address xxxxxxxx b initial value r/w a1 a0 r/w r/w r/w a4 a3 a2 r/w madr 1 to 6 (multi-address i 2 c address registers 1 to 6) r/w r/w r/w : read/write enabled x : undefined
420 chapter 16 multi-address i 2 c 16.4.5 multi-address i 2 c data register (mdar) the mdar register is used to set transmission data and to store received data. n multi-address i 2 c data register (mdar) figure 16.4-6 multi-address i 2 c data register (mdar) in master mode, the data written in the register is shifted to the sda line bit by bit from the msb bit. the write side in this register is made up of a double buffer. when the bus is in use (mbsr: bb = 1), written data is loaded to the eight-bit shift register when the transfer of the present byte is completed. the data in the shift register is shifted and output to the sda line bit by bit. the value written to this register has no effect on the present data transfer. also in slave mode, the same function can be used after the address is determined. when mbcr: int = 1 at data reception (mbsr: trx = 0), the received data can be read from this register. since the register for serial transfer is read directly in read cycle, the received data is effective only when mbcr: int = 1. d7 d5 d6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 9 h address xxxxxxxx b initial value r/w d1 d0 r/w r/w r/w r/w d4 d3 d2 r/w mdar (multi-address i 2 c data register) r/w r/w r/w : read/write enabled x : undefined
421 16.4 registers of the multi-address i 2 c 16.4.6 multi-address i 2 c timeout control register (mtcr) the mtcr register is used to control the sm bus timeout detection. n multi-address i 2 c timeout control register (mtcr) figure 16.4-7 "multi-address i 2 c timeout control register (mtcr)" shows the bit configuration of the multi-address i 2 c timeout control register (mtcr) figure 16.4-7 multi-address i 2 c timeout control register (mtcr) toe bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 a h address x0000000 b initial value ext ts1 ts0 ts2 r/w r/w r/w r/w r/w ts2 0 0 0 0 1 1 1 1 ts1 0 0 1 1 0 0 1 1 ts0 0 1 0 1 0 1 0 1 timeout count clock selection bit (t) timeout detection is not allowed timeout detection clock 1 x (t inst/2) timeout detection clock 2 x (t inst/2) timeout detection clock 3 x (t inst/2) timeout detection clock 4 x (t inst/2) timeout detection clock 5 x (t inst/2) timeout detection clock 6 x (t inst/2) timeout detection clock 7 x (t inst/2) ext timeout detection extended bit timeout is detected only in master/slave mode timeout is detected also in other than master/slave mode toe 0 1 timeout interrupt bit disables interrupts enables interrupts 0 1 - aac - aac 0 1 ack control bit at addressing ack output is not allowed ack is output automatically r/w r/w x : read/write enabled : undefined : initial value
422 chapter 16 multi-address i 2 c table 16.4-4 function of each bit in multi-address i 2 c bus status register (mtcr) bit name function bit 7 unused bit the read value is undefined. writing has no efect on operation. bit 6 aac: ack control bit at addressing this bit controls ack at address matching. when this bit is set to "1", ack control is performed automatically. (ack is returned automatically when the addresses 1 to 5 match. when "0" is written to this bit, ack at addressing is not output. bit 5 test bit this bit is a test bit. write "1" when multi-address i 2 c is used. note: though the initial value of this bit is "0", write "1" to this bit when multi-address i 2 c is used. bit 4 toe: timeout interrupt enable bit this bit enables/disables timeout interrupts. when "1" is written to this bit, timeout interrupts are enabled and an interrupt request is sent to the cpu. when "0" is written to this bit, timeout interrupts are disabled. bit 3 ext: timeout detection extended bit this bit makes extended control for detecting a timeout. when "1" is written to this bit, the timeout detection function also operates in a mode other than master/slave mode. when "0" is written to this bit, the timeout detection function operates only in master/slave mode. note: this bit is effective only when timeout detection is enabled (mtcr: ts0 to ts2 is other than "000".) bit 2 bit 1 bit 0 ts2, ts1, ts0: timeout count selection bits (t) these bits select the clock for detecting a timeout. when ts2 = 0, ts1 = 0, and ts0 = 0, the timeout detection function is disabled. with the clock selected in these bits [t x (t inst /2) x 10], the low period in the scl1 and sda1 lines is counted.
423 16.4 registers of the multi-address i 2 c 16.4.7 multi-address i 2 c timeout status register (mtsr) the mtsr register indicates the sm bus timeout detection status. n multi-address i 2 c timeout status register (mtsr) 16.4-8 "multi-address i 2 c timeout status register (mtsr)" shows the bit configuration of the multi-address i 2 c timeout status register (mtsr). figure 16.4-8 multi-address i 2 c timeout status register (mtsr) tdr str bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 b h address xxxx0000 b initial value mtr r/w r/w r/w r/w mtr master timeout interrupt request flag no master timeout a master timeout is detected 0 1 tcr 0 1 timeout clock interrupt request flag no timeout a timeout is detected str 0 1 slave timeout interrupt request flag no slave timeout a slave timeout is detected tcr - -- - tdr 0 1 timeout data interrupt request flag no timeout a timeout is detected r/w : read/write enabled x : undefined : initial value
424 chapter 16 multi-address i 2 c table 16.4-5 function of each bit in multi-address i 2 c timeout status register (mtsr) bit name function bit 7 bit 6 bit 5 bit 4 unused bits the read value is undefined. writing has no efect on operation. bit 3 tdr: timeout data interrupt request flag this bit detects a timeout of the data line. when timeout data is detected, this bit is set to "1". if timeout interrupts (mtcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no significance. bit 2 tcr: timeout clock interrupt request flag this bit detects a timeout of the clock line. when a timeout clock is detected, this bit is set to "1". if timeout interrupts (mtcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no significance. bit 1 mtr: master timeout interrupt request flag this bit detects a master timeout. when a master timeout is detected, this bit is set to "1". if master timeout interrupts (mtcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no meaning. bit 0 str: slave timeout interrupt request flag this bit detects a slave timeout. when a slave timeout is detected, this bit is set to "1". if slave timeout interrupts (mtcr: toe) are enabled at this time, an interrupt occurs. ? when a timeout is detected, this bit is cleared to "0". ? "1" written to this bit has no significance.
425 16.4 registers of the multi-address i 2 c 16.4.8 multi-address i 2 c timeout data register (mtod) the mtod register is used to detect an sm bus timeout (data line). n multi-address i 2 c timeout data register (mtod) figure 16.4-9 "multi-address i 2 c timeout data register (mtod)" shows the bit configuration of the multi-address i 2 c timeout data register (mtod) figure 16.4-9 multi-address i 2 c timeout data register (mtod) if the value written to this register plus one matches the counted value of the low time period of the sda1 line when the timeout detection function is enabled (mtcr: ts0 to ts2 is other than "000"), the timeout data interrupt request flag (mtsr: tdr) is set to "1". the low time period of the sda1 line is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 20. when the sda1 line is at a high level, the counter value is cleared to "0", and counting starts again when the sda1 line is at a low level. when the counter value matches "the value set in the timeout data register (mtod) + 1", a timeout is detected and the timeout data interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 c h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
426 chapter 16 multi-address i 2 c 16.4.9 multi-address i 2 c timeout clock register (mtoc) the mtoc register is used to detect an sm bus timeout (clock line). n multi-address i 2 c timeout clock register (mtoc) figure 16.4-10 "multi-address i 2 c timeout clock register (mtoc)" shows the bit configuration of the multi-address i 2 c timeout clock register (mtoc) figure 16.4-10 multi-address i 2 c timeout clock register (mtoc) if the value written to this register plus one matches the counted value of the low time period of the scl1 line when the timeout detection function is enabled (mtcr: ts0 to ts2 is other than "000"), the timeout clock interrupt request flag (mtsr: tcr) is set to "1". the low time period of the scl1 line is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 20. when the scl1 line is at a high level, the counter value is cleared to "0" and counting starts again when the scl1 line is at a low level. when the counter value matches "the value set in the timeout clock register (mtoc) + 1", a timeout is detected and the timeout clock interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 d h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
427 16.4 registers of the multi-address i 2 c 16.4.10 multi-address i 2 c master timeout register (mmto) the mmto register is used to detect an sm bus timeout. n multi-address i 2 c master timeout register (mmto) figure 16.4-11 "multi-address i 2 c master timeout register (mmto)" shows the bit configuration of the multi-address i 2 c master timeout register (mmto) figure 16.4-11 multi-address i 2 c master timeout register (mmto) when the value written to this register plus one matches the cumulative value of the low time period of the scl1 line counted from start to acknowledge (or from acknowledge to acknowledge or from acknowledge to stop) when the timeout detection function is enabled (mtcr: ts0 to ts2 is other than "000"), the master timeout interrupt request flag (mtsr: mtr) is set to "1". the low time period of the scl1 line is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 10. in master mode, the low time period cumulative value of the scl1 line is counted only when the scl1 line is at a low level and counting is stopped when the scl1 line is at a high level. at start, acknowledge or stop, or by exiting the master mode, the counter value is cleared to "0". when the counter value matches "the value set in the master timeout register (mmto) + 1", a master timeout is detected and the master timeout interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 e h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
428 chapter 16 multi-address i 2 c 16.4.11 multi-address i 2 c slave timeout register (msto) the msto register is used to detect an sm bus timeout. n multi-address i 2 c slave timeout register (msto) figure 16.4-12 "multi-address i 2 c slave timeout register (msto)" shows the bit configuration of the multi-address i 2 c slave timeout register (msto) figure 16.4-12 multi-address i 2 c slave timeout register (msto) when the value written to this register plus one matches the cumulative value of the low time period of the scl1 line counted from start to stop when the timeout detection function is enabled (mtcr: ts0 to ts2 is other than "000"), the slave timeout interrupt request flag (mtsr: str) is set to "1". the low-time period of the scl1 line is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) divided by 10 and the counter is incremented by the clock further divided by 20. in slave mode, the low-time period cumulative value of the scl1 line is counted only when the scl1 line is at a low level and counting is stopped when the scl1 line is at a high level. at start or stop or by exiting the slave mode, the counter value is cleared to "0". when the counter value matches "the value set in the slave timeout register (msto) + 1", a slave timeout is detected and the slave timeout interrupt request flag is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 4 f h address xxxxxxxx b initial value r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled x : undefined
429 16.4 registers of the multi-address i 2 c 16.4.12 multi-address i 2 c alert register (malr) the malr register is used for an sm bus alert signal. n multi-address i 2 c alert register (malr) figure 16.4-13 "multi-address i 2 c alert register (malr)" shows the bit configuration of the multi-address i 2 c alert register (malr). figure 16.4-13 multi-address i 2 c alert register (malr) when the alert detection permission bit is set to on (malr: aen = 1) and the alert_ack permission bit is set to "enabled" (malr:arae = 1), ack is returned and the alert request flag (malr:arf) is set when data set in the multi-address i 2 c address register 6 (alert command: 0001 100) is detected. when the alert detection permission bit is on (malr: aen = 1) and the alert request output bit is set to on (malr:aro = 1), an alert request is output from the p32/alert pin ("l" output). "alert command-0001 100" should already be set to multi-address i 2 c address register 6. the alert_ack permission bit (malr: arae) can control ack when addressing for address 6. when "0" is written in the bit, ack at addressing for address 6 is not output if the addresses are identical. if the bit is "1," ack control at addressing time for address 6 is done automatically. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 0 h xxxx0000 b - arf aen - r/w r/w r/w - - aro r/w arae address initial value r/w : read/write enabled x : undefined
430 chapter 16 multi-address i 2 c 16.5 multi-address i 2 c interrupts the multi-address i 2 c interface may generate an interrupt request when the data transfer is completed, a bus error has occurred, or a timeout is detected. n interrupt at bus error when the following conditions are met, a bus error is assumed to have occurred and the multi- address i 2 c interface is stopped. 1. when a stop condition is detected in master mode. 2. when a start or stop condition is detected when the first byte is being transmitted and received. 3. when a start or stop condition is detected when data (excluding the first bit of start, stop, and data) is being transmitted and received. if the bus error interrupt request enable bit is enabled (mbcr: beie = 1) at this time, an interrupt request is output to the cpu. clear the interrupt request by writing "0" to the ber bit in the interrupt processing routine. if a bus error has occurred in spite of the beie bit value, the ber bit is set to "1". regardless of the beie bit value, the ber bit is set to "1" if a bus error occurs. n interrupt at data transfer completion when data transfer is completed and the transfer end interrupt request enable bit is enabled (mbcr: inte = 1), an interrupt request (irqb) is output to the cpu. clear the interrupt request by writing "0" to the int bit in the interrupt processing routine. if data transfer is completed in spite of the inte bit value, the int bit is set to "1". n interrupt at timeout detection if the specified timeout time has expired when the timeout detection function is enabled (mtcr: ts0 to ts2 is other than "000"), a timeout interrupt is generated (irqc). the timeout can be checked with each interrupt request flag of the multi-address i 2 c bus status register (mtsr). when the timeout detection extended bit (mtor: ext) is set, the bus is also monitored in a mode other than master/slave mode.
431 16.5 multi-address i 2 c interrupts n register and vector table address related to interrupt of multi-address i 2 c for interrupt operation, see section 3.4.2 "interrupt processing. table 16.5-1 registers and vector table addresses related to interrupt of multi-address i 2 c interrupt name interrupt level setting register vector table address register bit to be set upper lower irqb ilr3 (007dh) lb1 (bit 7) lb90 (bit 6) ffe4h ffe5h irqc ilr4 (007eh) lc1 (bit 1) lc0 (bit 0) ffe2h ffe3h
432 chapter 16 multi-address i 2 c 16.6 operation of the multi-address i 2 c the multi-address i 2 c interfaceis a serial data base of 8-bit data synchronized with the shift clock. n multi-address i 2 c system m operation mode the multi-address i 2 c bus system uses a serial data line (sda) and a serial clock line (scl) to transfer data. all connected devices require an open-drain or open collector output. the logic function is used by connecting a pull-up resistor. each device connected to the bus has a unique address and can be set by software. among the devices, simple master/slave relations are established and master devices function as master transmitters or master receivers. the multi-address i 2 c interface is a full-fledged multi- master bus equipped with collision detection and arbitration functions so that data destruction can be prevented even if two or more masters attempt to start data transfer simultaneously. n multi-address i 2 c protocol figure 16.6-1 "data transfer example" shows the format required for data transfer. figure 16.6-1 data transfer example after a start condition (s) is generated, a slave address is transmitted. this address is a seven- bit address followed by a data direction bit (r/w) as 8th bit. data transfer is always ended with the master stop condition (p). it is also possible to address to another slave without generating a stop condition by generating a repeated start condition (sr). sda scl 7-bit address r/w lsb msb msb lsb stop condition no acknowledgement 8-bit address acknowledgement bit start condition
433 16.6 operation of the multi-address i 2 c n start condition when the master is not connected to the bus (the logic of scl and sda is "h") in states where the bus is released, the master generates a start condition. as indicated in figure 16.6-1 "data transfer example", a start condition is generated when the sda line is changed from "h" to "l" in states where scl is at the "h" level. at this time, new data transfer starts and master/slave operation starts. the two methods for generating a start condition are shown as follows. ? writing "1" to the mbcr: mss bit in states where the multi-address i 2 c bus is not used (mbcr: mss = 0, mbsr: bb = 0, mbcr: int = 0, mbsr: al = 0). thereafter, mbsr: bb is set to "1" to indicate bus busy. ? writing "1" to the mbcr: scc bit in interrupt states in bus master mode (mbcr: mss = 1, mbsr: bb = 1, mbcr: int = 1, mbsr: al = 0) and generates a repeated start condition. even if "1" is written to the mbcr: mss bit or "1" is written to the mbcr: scc bit under conditions other than the above conditions, it is ignored. if "1" is written to the mbcr: mss bit when another system is using the bus (in idle state), the mbsr: al bit is set to "1". n addressing in master mode, the bb and trx bits in the mbsr register are set to 1 after a start condition is generated and the contents of the mdar register in the slave address are output from the msb in turn. this address data consists of 8-bits with a seven-bit slave address, followed by a r/w bit indicating the data transfer direction (bit 0 in mdar). after the address data is transmitted, the master receives acknowledge from the slave. the sda line is set to "l" by the 9th clock and the master receives the acknowledge bit from the receiving end (see figure 16.6-1 "data transfer example"). at this time, the r/w bit (mdar: bit 0) is reversed and stored in the mbsr: trx bit. in slave mode, the bb and trx bits in the mbsr register are set to "1" and "0", respectively, after a start condition is detected and data from the master is received by the mdar register. after receiving the address data, the mdar and madr1 to 6 registers are compared. if the values match, mbsr: aas is set to "1" and acknowledge is transmitted to the master. thereafter, bit 0 of the received data (bit 0 in the mdar register) is stored in the mbsr: trx bit. n data transfer after addressing of the slave is achieved, data can be transmitted and received in byte units in the direction determined by the r/w bit sent by the master. each byte output to the sda line is fixed to 8-bits. as shown in figure 16.6-1 "data transfer example", the receiving device transmits acknowledge to the transmitting device by stabilizing the sda line to the "l" level when the acknowledge clock pulse is "h". with the msb at the head, each bit of data is transmitted in one clock pulse. each time a byte is transferred, acknowledge must be transmitted and received. therefore, 9 clock pulses are required to transfer one complete data byte. n acknowledge acknowledge is transmitted from the receiving end for the 9th clock of data byte transfer from the transmitting end. when data is received, the acknowledge bit can be enabled (mbcr: ack = 1) or disabled (mbcr: ack = 0) with the mbcr: ack bit. when transmitting data, acknowledge from the receiving end is stored in the mbsr: lrb bit.
434 chapter 16 multi-address i 2 c n stop condition by generating a stop condition, the master can release the bus to terminate communication. a stop condition can be generated by changing the sda line from "l" to "h" when the scl line is at the "h" level. it is a signal to notify the bus connection device of the end of communication (bus free) in master mode. the master can generate start conditions continuously without generating a stop condition. this is called the repeated start condition. in bus master mode, a stop condition is generated by writing "0" to the mbcr: mss bit in the interrupt state (mbcr: mss = 1, mbsr: bb = 1, mbcr: int = 1, mbsr: al = 0) and the master mode is switched to the slave mode.. even if "0" is written to the mbcr: mss bit in other the above, it is ignored. n arbitration this interface circuit is a full-fledged multi-master bus that can connect two or more masters. if a master transfers data and another master transfers data simultaneously, an arbitration is generated. an arbitration occurs in the sda line when the scl line is at the "h" level. the master recognizes the occurrence of an arbitration lost when its transmission data is "1" and data on the sda line is at the "l" level, and then it sets data output to off and sets the mbsr: al bit to "1". when the mbsr: al is set to "1", "0" is written to mbcr: mss and mbsr: trx. as a result, the trx is cleared and the master mode is switched to the slave reception mode.
435 16.7 notes on using the multi-address i 2 c 16.7 notes on using the multi-address i 2 c this section describes precautions to take when using the multi-address i 2 c interface. n precaution in setting the multi-address i 2 c interface register before writing to the bus control register (mbcr), the multi-address i 2 c interface must be enabled (mccr: en). when the master slave selection bit (mbcr: mss) is set, transfer starts. n precaution in setting shift clock frequency to calculate the shift clock frequency using the f sck expression (1) in table 16.4-3 "function of each bit in multi-address i 2 c clock control register (mccr)", it is necessary to know the values of m, n, and dmbp. when the value of m is 5 (mccr: cs4 = cs3 =0) and the value of n is 4 (mccr: cs2 = cs1 = cs0 = 0), "dmbp = 1" cannot be selected. other combinations do not present a problem. n precaution on the priority at simultaneous writing ? contention of the next byte transfer and stop condition when "0" is written to mbcr: mss in states where mbcr: int is cleared, the mss bit has a higher priority and a stop condition is generated. ? contention of the next byte transfer and start condition when "1" is written to mbcr: scc in states where mbcr: int is cleared, the scc bit has a higher priority and a start condition is generated. n precaution on setting with software do not select the repeated start condition (mbcr: en = 0) and the slave mode (mbcr: mss = 0) at the same time. in states where the interrupt request flag bits (ber and int in the mbcr register) are set to "1" and the interrupt request enable bits are enabled (beie and inte in the mbcr register are set to "1"), recovery from the interrupt processing cannot be performed. clear the ber and int bits in the mbcr register. when the multi-address i 2 c operation is not permitted (mccr: en = 0), all bits of the bus status register mbsr and the bus control register mbcr (excluding the bus error ber bit and the bus error enable beie bit) are cleared.
436 chapter 16 multi-address i 2 c 16.8 operation of the timeout detection function this section describes the operation of the timeout detection function when it is used as the sm bus. n data timeout when the "l" period of the sda1 line exceeds 25 ms, this state is defined as a data timeout. the low time period is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 20. when the counter value matches "the value set in the timeout data register (mtod) + 1", a timeout is detected and the timeout data interrupt request flag (mtsr: tdr) is set. figure 16.8-1 data timeout n clock timeout when the "l" period of the scl1 line exceeds 25 ms, this state is defined as a clock timeout. the low-time period is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 20. when the counter value matches "the value set in the timeout clock register (mtoc) + 1", a timeout is detected and the timeout clock interrupt request flag (mtsr: tcr) is set. figure 16.8-2 clock timeout sda1 data timeout 25 ms or longer scl1 clock timeout 25 ms or longer
437 16.8 operation of the timeout detection function n master timeout when the cumulative "l" period of the scl1 line between one byte data (start to ack, ack to ack, ack to stop) exceeds 10 ms in master mode, this state is defined as a master timeout. the low-time period is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 10. when the counter value matches "the value set in the master timeout register (mmto) + 1", a master timeout is detected and the master timeout interrupt request flag (mtsr: mtr) is set. figure 16.8-3 master timeout scl1 master timeout 10 ms or longer start ack
438 chapter 16 multi-address i 2 c n slave timeout when the cumulative "l" period in the scl1 line between start and stop exceeds 10 ms in slave mode, this state is defined as a slave timeout. the low-time period is counted with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) (t) divided by 10 and the counter is incremented by the clock further divided by 20. when the counter value matches "the value set in the slave timeout register (msto) + 1", a slave timeout is detected and the slave timeout interrupt request flag (mtsr: str) is set. figure 16.8-4 slave timeout scl1 slave timeout 25 ms or longer start stop
439 16.8 operation of the timeout detection function n timeout clock supply block figure 16.8-5 "timeout clock supply block" shows the clock supply block of timeout. figure 16.8-5 timeout clock supply block n errors timeout detection is performed with the clock selected with the timeout count clock detection bits (mtcr: ts0 to ts2) (t) divided by 10. therefore, the following errors occur in the detection of an "l" width when, for example, t = 0.5 m s. ? detects an "l" width of 5 to 5.5 m s or more in duration. (the sampling cycle is 0.5 m s) ? when the count is stopped (when low width detection is completed), an error of up to -5.5 m s in duration occurs. (in a cumulative count, errors are also accumulated.) the counter for detecting a timeout is incremented with an l width or cumulative l width of 100 m s or more (50 m s or more for a master timeout). ts0,1,2 scl1 line sda2 low detection divide-by-10 clr divide-by-20 clr h detection first byte detection start detection stop detection divide-by-10 counter clr mtoc comp counter clr mmto comp divide-by-20 counter clr msto comp clr clr sda1 line sda2 low detection low width detection low width detection divide-by-10 clr t inst 2 t= divide-by-20 clr h detection counter data timeout detected clock timeout detected master timeout detected slave timeout detected clr mtod comp
440 chapter 16 multi-address i 2 c
441 chapter 17 bridge circuit this chapter describes the functions and operations of the bridge circuit. 17.1 "overview of the bridge circuit" 17.2 "configuration of the bridge circuit" 17.3 "pins of the bridge circuit 17.4 "registers of the bridge circuit"
442 chapter 17 bridge circuit 17.1 overview of the bridge circuit the bridge circuit is used to switch the i/o path of the i 2 c/uart. n bridge circuit m selection of "i 2 c", multi-address i 2 c, or "uart" the bridge circuit can switch the i/o path of each port to "i 2 c", "multi-address i 2 c, and "uart". table 17.1-1 "ports and target units that can be selected by the bridge circuit" lists the ports and target units that can be selected by the bridge circuit. m bypass with p30 - p31 in the bridge circuit, p30/scl1 - p31/sda1 can be bypassed with other buses (p33/scl2 - p34/sda2, p40/scl3 - p41/sda3, and p42/scl4 - p43/sda4). table 17.1-1 ports and target units that can be selected by the bridge circuit ports that can be selected by the bridge circuit target units p33/scl2/uck3 p34/sda2/ui3 (p35/u03) i 2 c uart multi-address i 2 c p40/scl3/uck1 p41/sda3/ui1 (p65/u01) i 2 c uart multi-address i 2 c p42/scl4/uck2 p43/sda4/ui2 (p64/u02) i 2 c uart multi-address i 2 c
443 17.2 configuration of the bridge circuit 17.2 configuration of the bridge circuit the bridge circuit consists of the following blocks. ? bridge circuit selection registers (brsr1 to 3) n bridge circuit block diagram figure 17.2-1 bridge circuit block diagram m bridge circuit selection registers 1 to 3 (brsr 1 to 3) these registers are used for switching the bridge circuit. i 2 c multi-address i 2 c p31/sda1 p30/scl1 p34/sda2/ui3 p33/scl2/uck3 p41/sda3/ui1 p40/scl3/uck1 p43/sda4/ui2 p42/scl4/uck2 brsr2 brsr1 i 2 c i/o bi3 bi2 bi4 bm3 bm2 bm4 bl2 bl3 bl4 uart bu1 bu3 bu2 p35/uo3 p65/uo1 p64/uo22 brsr3
444 chapter 17 bridge circuit 17.3 pins of the bridge circuit this section describes the pins related to the bridge circuit. it also shows a block diagram of pins. n pins related to the bridge circuit the pins related to the bridge circuit are as follows: p33/scl2/uck3, p34/sda2/ui3, p35/uo3, p40/scl3/uck1, p41/sda3/ui1, p65/uo1, p42/ scl4/uck2, p43/sda4/ui2, and p64/uo2 pins. p33/scl2/uck3, p34/sda2/ui3, and p35/uo3 pins each of these pins has multiple functions. each pin can act as a general-purpose i/o- dedicated port (p33, p34, p35), i 2 c i/o pin (scl2, sda2), or uart/sio i/o pin (uck3, ui3, uo3). the pin status can be read directly from the port data register (pdr3). p40/scl3/uck1, p41/sda3/ui1, and p65/uo1 pins each of these pins has multiple functions. each pin can act as a general-purpose i/o- dedicated port (p40, p41, p65), i 2 c i/o pin (scl3, sda3), or uart/sio i/o pin (uck1, ui1, uo1). the pin status can be read directly from the port data registers (pdr4 and pdr6). p42/scl4/uck2, p43/sda4/ui2, and p64/uo2 pins each of these pins has multiple functions. each pin can act as a general-purpose i/o- dedicated port (p42, p43, p64), i 2 c i/o pin (scl4, sda4), or uart/sio i/o pin (uck2, ui2, uo2). the pin status can be read directly from the port data registers (pdr4 and pdr6). figure 17.3-1 "a block diagram of the pins related to the bridge circuit" shows the pins related to the bridge circuit.
445 17.3 pins of the bridge circuit n block diagram of pins related to the bridge circuit figure 17.3-1 a block diagram of the pins related to the bridge circuit pdr write output latch stop/watch mode (spl=1) pdr (port data register) internal data bus pin n-ch pdr read stop/watch mode from the resource (lcd) output enable bit from resource (lcd) output uart output from the bridge circuit p65/uo1 p64/uo2 spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions) i 2 c output i 2 c input from the bridge circuit from the bridge circuit from the bridge circuit from the bridge circuit multi-address i 2 c input multi-address i 2 c output output tr. uart output(p33,p40,p42 only) p33/scl2/uck3 p34/sda2/ui3 p40/scl3/uck1 p41/sda3/ui1 p42/scl4/uck2 p43/sda4/ui2 internal data bus pdr (port data register) pdr write output latch pdr read stop/watch mode (spl=1) uart input stop/watch mode stop/watch mode stop/watch mode pin pin spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
446 chapter 17 bridge circuit output tr. p35/uo3 internal data bus pdr (port data register) output latch pdr write stop/watch mode (spl=1) pdr read uart output from the bridge circuit stop/watch mode pin spl: pin state designate bit of the standby control register (stbc) pdr read (for bit manipulation instructions)
447 17.4 registers of the bridge circuit 17.4 registers of the bridge circuit this section shows the registers related to the bridge circuit. n registers related to bridge circuit figure 17.4-1 registers related to bridge circuit brsr1 (bridge circuit selection register 1) brsr2 (bridge circuit selection register 2) brsr3 (bridge circuit selection register 3) r/w : read/write enabled x : undefined bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 c h address xxxxx000 b initial value bl3 bl4 - - - - - r/w r/w r/w bl2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 d h xx000000 b bm2 bi3 r/w r/w r/w r/w r/w bi4 bm4 bm3 r/w bi2 address initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 9 h xxxxx001 b bu2 bu3 r/w r/w r/w bu1 address initial value - - - - -
448 chapter 17 bridge circuit 17.4.1 bridge circuit selection register 1 ( brsr1) bridge circuit selection register 1 (brsr1) is used to control bypass between the pins by the bridge circuit. n bridge circuit selection register 1 (brsr1) figure 17.4-2 bridge circuit selection register 1 (brsr1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 c h address xxxxx000 b initial value bl3 bl4 - - - - - r/w r/w r/w bl2 bridge circuit pin bypass selection 2 cut "p30 and p33" and "p31 and p34" bypass "p30 and p33" and "p31 and p34" bl2 0 1 bridge circuit pin bypass selection 3 cut "p30 and p40" and "p31 and p41" bypass "p30 and p40" and "p31 and p41" bl3 0 1 bridge circuit pin bypass selection 4 cut "p30 and p42" and "p31 and p43" bypass "p30 and p42" and "p31 and p43" bl4 0 1 r/w : read/write enabled x : undefined : initial value table 17.4-1 bridge circuit register 1 (brsr1) bit functions bit name function bit 7 bit 6 bit 5 bit 4 bit 3 unused bits ? the read value is undefined. ? writing has no effect on operation.
449 17.4 registers of the bridge circuit bit 2 bl4: bridge circuit pin bypass selection 4 this bit controls bypass setting for "p30/scl1 and p42/ scl4" and "p31/ sda1 and p43/sda4". when "1" is written in this bit, bypass is set. ? p30/scl1 = p42/scl4/uck2 ? p31/sda1 = p43/sda4/ui2 when "0" is written in this bit, bypass is cut. ? p30/scl1 not equal to p42/scl4/uck2 ? p31/sda1 not equal to p43/sda4/ui2 bit 1 bl3: bridge circuit pin bypass selection 3 this bit controls bypass setting for "p30/scl1 and p40/ scl3" and "p31/ sda1 and p41/1sda3". when "1" is written in this bit, bypass is set. ? p30/scl1 = p40/scl3/uck1 ? p31/sda1 = p41/1sda3/ui1 when "0" is written in this bit, bypass is cut. ? p30/scl1 not equal to p40/scl3/uck1 ? p31/sda1 not equal to p41/1sda3/ui1 bit 0 bl2: bridge circuit pin bypass selection 2 this bit controls bypass setting for "p30/scl1 and p31/ scl2" and "p31/ sda1 and p34/sda2". when "1" is written in this bit, bypass is set. ? p30/scl1=p33/scl2/uck3 ? p31/sda1=p34/sda2/ui3 when "0" is written in this bit, bypass is cut. ? p30/scl1 not equal to p33/scl2/uck3 ? p31/sda1 not equal to p34/sda2/ui3 table 17.4-1 bridge circuit register 1 (brsr1) bit functions (continued) bit name function
450 chapter 17 bridge circuit 17.4.2 bridge circuit selection register 2 (brsr2) bridge circuit selection register 2 (brsr2) controls the connection switching by the bridge circuit. n bridge selection register 2 (brsr2) figure 17.4-3 bridge circuit selection register 2 (brsr2) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 d h xx000000 b bm2 bi3 r/w r/w r/w r/w r/w bi4 bm4 bm3 r/w bi2 bm3 0 0 1 1 bridge circuit selection 3 use p40 and p41 as a "port" connect p40 and p41 to the i 2 c connect p40 and p41 to the multi-address i 2 c use p40 and p41 as a "port" bi3 0 1 0 1 bm4 0 0 1 1 bridge circuit selection 4 use p42 and p43 as a "port" connect p42 and p43 to the i 2 c connect p42 and p43 to the multi-address i 2 c use p42 and p43 as a "port" bi4 0 1 0 1 bm2 0 0 1 1 bridge circuit selection 2 use p33 and p34 as a "port" connect p33 and p34 to the i 2 c connect p33 and p34 to the multi-address i 2 c use p33 and p34 as a "port" bi2 0 1 0 1 address initial value r/w : read/write enabled x : undefined : initial value
451 17.4 registers of the bridge circuit note: switching of the connection destination by this register is valid only when the resource function of the connection destination has been allowed. be careful not to duplicate the port specification for switching the connection destination between this register and the brsr3 register. table 17.4-2 bridge circuit selection register 2 (brsr2) bit functions bit name function bit 7 bit 6 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 5 bm4: bridge circuit multi-i 2 c selection 4 this bit specifies options for p42/scl4/uck2 and p43/ sda4/ui2 whether they are connected to the "multi-address i 2 c." when "1" is written in this bit, p42/scl4 and p43/sda4 are connected to the "multi-address i 2 c." when this bit is "0" or bm4=bi4=1, the port function is selected. bit 4 bi4: bridge circuit i 2 c selection 4 this bit specifies options for p42/scl4/uck2 and p43/ sda4/ui2 whether they are connected to the "i 2 c." when "1" is written in this bit, p42/scl4 and p43/sda4 are connected to the "i 2 c." when this bit is "0" or bm4=bi4=1, the port function is selected. bit 3 bm3: bridge circuit multi-i 2 c selection 3 this bit specifies options for p40/scl3/uck1 and p41/ sda3/ui1 whether they are connected to the "multi-address i 2 c." when "1" is written in this bit, p40/scl3 and p41/sda3 are connected to the "multi-address i 2 c." when this bit is "0" or bm3=bi3=1, the port function is selected. bit 2 bi3: bridge circuit i 2 c selection 3 this bit specifies options for p40/scl3/uck1 and p41/ sda3/ui1 whether they are connected to the "i 2 c." when "1" is written in this bit, p40/scl3 and p41/sda3 are connected to the "i 2 c." when this bit is "0" or bm3=bi3=1, the port function is selected. bit 1 bm2: bridge circuit multi-i 2 c selection 2 this bit specifies options for p33/scl2/uck3 and p34/ sda2/ui3 whether they are connected to the "multi-address i 2 c." when "1" is written in this bit, p33/scl2 and p34/sda2 are connected to the "multi-address i 2 c." when this bit is "0" or bm2=bi2=1, the port function is selected. bit 0 bi2: bridge circuit i 2 c selection 2 this bit specifies options for p33/scl2/uck3 and p34/ sda2/ui3 whether they are connected to the "i 2 c." when "1" is written in this bit, p33/scl2 and p34/sda2 are connected to the "i 2 c." when this bit is "0" or bm2=bi2=1, the port function is selected.
452 chapter 17 bridge circuit 17.4.3 bridge circuit selection register 3 (brsr3) bridge circuit selection register (brsr3) controls connection switching by the bridge circuit. n bridge circuit selection register 3 (brsr3) figure 17.4-4 bridge circuit selection resister 3(brsr3) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 9 h xxxxx001 b bu2 bu3 r/w r/w r/w bu1 bridge circuit uart selection 1 use p40, p41, and p65 as a "port" connect p40, p41, and p65 to "uart" bu1 0 1 bridge circuit uart selection 2 use p42, p43, and p64 as a "port" connect p42, p43, and p64 to "uart" bu2 0 1 bridge circuit uart selection 3 use p33, p34, and p35 as a "port" connect p33, p34, and p35 to "uart" bu3 0 1 address initial value r/w : read/write enabled x : undefined : initial value - - - - -
453 17.4 registers of the bridge circuit note: switching of the connection destination is valid only when the resource function of the connection destination has been allowed. be careful not to duplicate the port specification for switching the connection destination between this register and the brsr3 register. table 17.4-3 bridge circuit selection register 3 (brsr3) bit functions bit name function bit 7 bit 6 bit 5 bit 4 bit 3 unused bits ? the read value is undefined. ? writing has no effect on operation. bit 2 bu3: bridge circuit uart selection 3 this bit specifies options for "p33/scl2/uck3, p34/sda2/ ui3, and p35/uo3" whether they are connected to uart. when "1" is written in this bit, uart is selected. ? uck3 (p33): acts as uck only when uart serial clock output is allowed (smc2:scke = 1). ? ui3 (p34) ? uo3 (p35): acts as uo only when uart serial data output is allowed (smc2:txoe = 1). when "0" is written in this bit, the port function is selected. bit 1 bu2: bridge circuit uart selection 2 this bit specifies options for "p42/scl4/uck2, p43/sda4/ ui2, and p64/uo2" whether thy are connected to uart. when "1" is written in this bit, uart is selected. ? uck2 (p42): acts as uck only when uart serial clock output is allowed (smc2:scke = 1). ? ui2 (p43) ? uo2 (p64): acts as uo only when uart serial data output is allowed (smc2:txoe = 1). when "0" is written in this bit, the port function is selected. bit 0 bu1: bridge circuit uart selection 1 this bit specifies options for "p40/scl3/uck1, p41/sda3/ ui1, and p65/uo1" whether they are connected to uart. when "1" is written in this bit, uart is selected. ? uck1 (p40): acts as uck only when uart serial clock output is allowed (smc2:scke = 1). ? ui1 (p41) ? uo1 (p65): acts as uo only when uart serial data output is allowed (smc2:txoe = 1). when "0" is written in this bit, the port function is selected.
454 chapter 17 bridge circuit
455 chapter 18 lcd controller driver this chapter describes the functions and operations of the lcd controller driver. 18.1 "overview of the lcd controller driver" 18.2 "configuration of the lcd controller driver" 18.3 "pins of the lcd controller driver" 18.4 "registers of the lcd controller driver" 18.5 "lcd display ram in the lcd controller driver" 18.6 "operation of the lcd controller driver"
456 chapter 18 lcd controller driver 18.1 overview of the lcd controller driver the lcd controller driver, which contains 8-byte display data memory, controls the lcd display with four common output signals and 14 segment output signals. by selecting from three types of duty output, the lcd panel can be driven directly. n lcd controller driver functions the lcd controller driver has a function for displaying the description of the display data memory (lcd display ram) on the lcd panel directly with the segment output pins and the common output pins. ? the lcd controller driver contains voltage dividing resistors for lcd driving. the external dividing resistors can also be connected to the lcd controller driver. ? up to four common output pins (com0 to com3) and 14 segment output pins (seg0 to seg13) can be used. ? the lcd controller driver contains a 7-byte (14 x 4 bit) lcd display ram. ? as duty, 1/2, 1/3, or 1/4 can be selected. (it is restricted by bias setting.) ? as a driving clock, a main clock or a subclock can be selected. ? the lcd can be driven directly. table 18.1-1 "combinations of bias and duty" shows available combinations of bias and duty. table 18.1-1 combinations of bias and duty bias 1/2 duty 1/3 duty 1/4 duty 1/2 bias yes no no 1/3 bias no yes yes yes: recommended mode no: unavailable
457 18.2 configuration of the lcd controller driver 18.2 configuration of the lcd controller driver the lcd controller driver consists of the following eight blocks, which can be divided into two sections in terms of functions: the controller section that generates segment and common signals in accordance with the description in the lcd display ram and the driver section that drives the lcd. ? lcdc control register 1 (lcr1) ? lcd display ram ? prescaler ? timing controller ? alternating current generating circuit ? common driver ? segment driver ? dividing resistors n lcd controller driver block diagram figure 18.2-1 lcd controller driver block diagram lcdc control register 1 (lcr1) timing controller lcd display ram 14 4 bits (7 bytes) internal data bus segment driver seg0 to seg13 com0 com1 com2 com3 common driver alternating current generating 4 controller f ch /2 8 subclock (32 khz) dividing resistors v0 v1 v2 v3 fc h : main clock oscillation frequency prescaler (time base timer output) lcdc control registers 2 to 4 (lcr2-4) 14 circuit
458 chapter 18 lcd controller driver m lcdc control register 1 (lcr1) this register selects a clock for generating frame cycles (driving duty), controls the lcd driving power supply, selects display or display blanking, selects the display mode, and selects the cycle of the lcd clock (duty driving). m lcdc display ram a 16 x 4 bit ram for generating segment output signals. the description in this ram is read in synch with the common signal selection timing automatically and is output from segment output pins. m prescaler the prescaler generates a frame frequency in accordance with the setting selected from two types of clocks and four types of frequencies. m timing controller the timing controller controls common signals and segment signals based on the frame frequency and the setting in the lcr1 register. m alternating current generating circuit this circuit generates an alternating current waveform for driving the lcd from the signals from the timing controller. m common driver a driver for the common pins in the lcd. m segment driver a driver for the segment pins in the lcd. m dividing resistors resistors for generating the lcd driving voltage by dividing a voltage. the dividing resistors can also be connected externally. n power supply voltage of the lcd controller driver the power supply voltage of the lcd driver is set using the internal dividing resistors or by connecting dividing resistors to the pins v0 to v3.
459 18.2 configuration of the lcd controller driver 18.2.1 internal dividing resistors of the lcd controller driver the supply voltage of the lcd controller driver is generated by the internal dividing resistors. (the dividing resistors can also be connected externally.) n internal dividing resistors the lcd controller driver contains internal dividing resistors. the external dividing resistors can also be connected to pins v0 to v3. the internal dividing resistors or the external dividing resistors can be selected with the driving power supply control bit in the lcdc control register 1 (lcr1: vsel). when the vsel bit is set to "1," the internal dividing resistors are energized. to use only the internal dividing resistors without using external dividing resistors, set this bit to "1." the lcd controller permission is inactivated at lcd operation stop (lcr1: ms1, ms0 = 00 b ) and in watch mode (stbc: tmd = 1) in states where operation in watch mode is prohibited (lcr: lcen = 0). to set 1/2 bias, short-circuit the v2 and v1 pins. figure 18.2-2 "equivalent circuit of the internal dividing resistors" shows the equivalent circuit of the internal dividing resistors. figure 18.2-2 equivalent circuit of the internal dividing resistors v2 v1 vcc v3 lcdc permission vsel v0 v2 v1 v3 v0 v0 to v3: voltages at v0 to v3 pins 2r r r r short-circuited at 1/2 bias p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch n-ch
460 chapter 18 lcd controller driver n using the internal dividing resistors when internal dividing registers are used, the voltages at v1, v2, and v3 become lower by 2r because a resistor (2r) is included. figure 18.2-3 "states in which the internal dividing resistors are used" shows the states in which the internal dividing resistors are used. figure 18.2-3 states in which the internal dividing resistors are used n adjusting the brightness of the lcd when the internal dividing resistors are used if the brightness cannot be increased when the internal dividing resistors are used, connect a variable register (vr) externally (between vcc and v3 pins) to adjust the voltage at 3v. figure 18.2-4 "brightness adjustment when the internal dividing resistors are used" shows a connection example of the vr. figure 18.2-4 brightness adjustment when the internal dividing resistors are used note: during lcd operation, the internal 2r is effective. therefore, vr and 2r are connected in parallel. vcc v3 v2 v1 v0 2r r r r n-ch n-ch lcd controller permission lcd controller permission vcc 2r r r r 1/2 bias 1/3 bias v3 v2 v1 v0 v3 v2 v1 v0 v3 v0 v0 to v3: voltages at v0 to v3 pins v2 v1 vcc 2r r r r n-ch when the brightness is to be adjusted v3 v2 v1 v0 v0 to v3: voltages at v0 to v3 pins v3 v2 v1 v0 vr lcd controller permission
461 18.2 configuration of the lcd controller driver 18.2.2 external dividing resistor of lcd controller driver external dividing resistors can be connected to the pins v0 to v3. by connecting a variable resistor between the vcc and v3 pins, the brightness level can be adjusted. n external dividing resistors the external dividing resistors can be connected to the lcd driving power supply pins (v0 to v3) instead of using the internal dividing resistors. the connection of external dividing resistors based on the bias method and the lcd driving voltages are shown in figure 18.2-5 "connection example of external dividing resistors" and table 18.2-1 "setting of lcd driving voltages", respectively. figure 18.2-5 connection example of external dividing resistors vcc v3 v2 v1 v0 vlcd 1/2 bias 1/3 bias vlcd vcc v3 v2 v1 v0 r r vr r r r vr table 18.2-1 setting of lcd driving voltages v3 v2 v1 v0 1/2 bias v lcd 1/2v lcd 1/2v lcd gnd 1/3 bias v lcd 2/3v lcd 1/3v lcd gnd v0 to v3: voltages at v0 to v3 pins v lcd : operating voltage of lcd
462 chapter 18 lcd controller driver n using external dividing resistors the v0 pin is internally connected to vss (gnd) through a transistor. therefore, when external dividing resistors are used, the current flowing into the resistor can be shut off when the lcd controller driver is stopped by connecting the vss of the dividing resistors to the v0 pin only. figure 18.2-6 "state where external dividing resistors are used" shows the external dividing resistors being used. figure 18.2-6 state where external dividing resistors are used 1. to connect dividing resisters externally without being affected by the internal dividing resistors, the entire internal dividing resistors must first be separated by writing "0" to the driving voltage control bit (lcr: vsel) in the lcd controller control register. 2. if a value other than "00b" is written to the display mode selection bits (ms1, ms0) in the lcr1 register in states where the internal dividing resistors are separated, the lcd controller enable transistor (q1) is set to "on" and current flows into the external dividing resistors. 3. if "00b" is written to the display mode selection bits (ms1, ms0) in the lcr1 register, the lcd controller enable transistor (q1) is set to "off" and current does not flow into the external dividing resistors. note: the rx connected externally differs depending on the lcd used. select an appropriate resistance. v3 v2 v1 v0 vcc v3 v2 v1 v0 2r r r r q1 vr rx rx rx v0 to v3: voltages at v0 to v3 pins lcd controller permission
463 18.3 pins of the lcd controller driver 18.3 pins of the lcd controller driver this section shows the pins related to the lcd controller driver and the block diagram of pins. n pins related to the lcd controller driver the pins related to the lcd controller driver include four common output pins (com0 to com3), 14 segment output pins (seg0 to seg13), and four power supply pins for lcd driving (v0 to v3). m pb4/com0 to pb7/com3 pins the pb4/com0 to pb7/com3 pins serve as an i/o port (pb4 to pb7) and lcd common output pins (com0 to com3) that can be switched with the lcr4 register. m pa0/seg00 to pa7/seg07 and p60/seg08 to p65/seg13 pins the p60/seg08 to p65/seg13 pins serve as an i/o port (p60 to p65) and lcd segment output pins (seg08 to seg13) that can be switched with the lcr2 register. the pa0/seg00 to pa7/ seg07 pins serve as i/o ports (pa0 to pa7) and lcd segment output pins (seg00 to seg07) that can be switched with the lcr3 register. m pb0/v0 to pb3/v3 pins the pb0/v0 to pb3/v3 pins serve as power pins for lcd driving (v0 to v3) and output pins (pb0 to pb3) that can be switched with the lcr4 register. note: to use these bits as lcdc pins, set the corresponding bits to "lcd enabled" with the lcdc control registers (lcr2, lcr3, and lcr4) and set the output transistor to "off" by writing "1" to the corresponding port data registers (pdr6, pdra, and pdrb).
464 chapter 18 lcd controller driver n block diagram of pins related to lcd controller driver figure 18.3-1 block diagram of pins related to lcd controller driver pdr write pin n-ch pa0/seg00 to pa7/seg07 p60/seg08 to p65/seg13 pb4/com0 to pb7/com3 pdr read stop/watch mode from resource output enable bit uart output from bridge circuit p64 and p65 only pins that also serve as segment output pins p-ch n-ch p-ch n-ch segment control signal lcd driving voltage (v3 or v2) lcd driving voltage (v1 or v0) segment control signal pdr write output latch output latch stop/watch mode (spl=1) stop/watch mode (spl=1) pdr (port data register) pdr (port data register) internal data bus internal data bus pin n-ch pb0/v0 to pb3/v3 lcdc power supply pdr read (for bit manipulation instructions) spl: pin state designate bit of the standby control register (stbc) spl: pin state designate bit of the standby control register (stbc)
465 18.4 registers of the lcd controller driver 18.4 registers of the lcd controller driver this section shows the registers related to the lcd controller driver. n registers related to lcd controller driver figure 18.4-1 registers related to lcd controller driver css vsel lcden bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 e h address 00010000 b initial value r/w fp1 fp0 r/w r/w r/w r/w bk ms1 ms0 r/w lcr1 (lcdc control register 1) r/w r/w - seg13 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 f h address x000000x b initial value r/w seg9 seg8 r/w r/w r/w seg12 seg10 r/w lcr2 (lcdc control register 2) r/w seg11 - bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 6 h address 00000000 b initial value r/w r/w r/w r/w r/w r/w lcr3 (lcdc control register 3) r/w r/w com2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 8 h address 0000xxxx b initial value r/w -- r/w com1 com3 r/w lcr4 (lcdc control register 4) r/w com0 - seg7 seg3 seg2 seg6 seg4 seg5 seg1 seg0 - r/w : read/write enabled
466 chapter 18 lcd controller driver 18.4.1 lcdc control register 1 (lcr1) the lcdc control register 1 (lcr1) selects a clock for generating frame cycles, controls the power supply for lcd driving, selects display or display blanking, selects the display mode, and selects the cycle of the lcd clock (duty driving). n lcdc control register 1 (lcr1) figure 18.4-2 lcdc control register 1 (lcr1) bk bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 5 e h address 00010000 b initial value ms1 fp1 fp0 ms0 r/w r/w r/w r/w r/w lcden css vsel r/w r/w r/w fp1 frame cycle selection bits fch / (2 13 x n)(305hz) fch / (2 14 x n)(153hz) fch / (2 15 x n) (76hz) fch /(2 16 x n) (37hz) f cl / (2 5 xn) (256hz) f cl / (2 6 xn) (128hz) f cl / (2 7 xn) (64hz) f cl / (2 8 xn) (32hz) 0 0 1 1 main clock (css = 0) subclock (css = 1) fp0 0 1 0 1 values in parentheses indicate the values when f ch = 10mhz, fcl = 32.768khz, and n = 4 n : no. of time divisions f ch : main clock oscillation frequency f cl : subclock oscillation frequency ms1 0 0 1 1 lcd operation stop 1/2 duty output mode (no. of time divisions n = 2) 1/3 duty output mode (no. of time divisions n = 3) 1/4 duty output mode (no. of time divisions n = 4) ms0 0 1 0 1 display mode selection bits bk display blanking selection bit display display blanking 0 1 css frame cycle generating clock selection bit main clock subclock 0 1 lcden watch mode time operation enable bit stops in watch mode operates in watch mode 0 1 vsel lcd driving power supply control bit external dividing resistors are used (internal dividing resistors are shut off) internal dividing resistors are used 0 1 r/w : read/write enabled : initial value
467 18.4 registers of the lcd controller driver table 18.4-1 functions of each bit in lcdc control register 1 (lcr1) bit name function bit 7 css: frame cycle generating clock selection bit ? this bit selects the clock for generating the lcd display frame cycle (for driving duty). ? when this bit is "0," the lcd controller driver is operated on the output of the time base timer that is the main clock oscillation frequency divided by 2 8 . when this bit is "1," it is operated on the subclock note: in main stop and subclock modes, the lcd controller driver cannot be operated on the output of the time base timer because oscillation of the main clock is stopped. to operate the lcd controller driver on the subclock, check that the subclock is fully stabilized before switching to the subclock. reference: even if the rate of the main clock is switched (gear function) when the lcd controller driver is operating on the timer base timer, the frame frequency is not affected. bit 6 lcden: watch mode time operation enable bit ? this bit selects whether the lcd controller driver is operated in watch mode. ? when this bit is "1," lcd display continues even after moving to the watch mode. ? when this bit is "0," lcd display is stopped in watch mode. note: to operate lcd display even in watch mode, the subclock (css = 1) must be selected. bit 5 vsel: lcd driving power supply control bit ? this bit selects whether the internal dividing resistors are energized. ? when this bit is "0," the internal dividing resistors are shut off; when this bit is "1," the resistors are energized. to connect external dividing resistors, this bit must be set to "0." bit 4 bk: display blanking selection bit ? this bit selects whether or not the lcd is displayed. ? in display blanking (non-display, bk = 1), the segment output indicates a non-selected waveform (a waveform that is out of the display condition). bit 3 bit 2 ms1, ms0: display mode selection bits ? these bits select the duty of the output waveform from three types. ? the operating common pins are determined in accordance with the selected duty output mode. ? when these bits are "00b," the lcd controller driver stops display. note: when the selected frame cycle generating clock stops due to a shift to the top mode or otherwise, stop the display operation in advance.
468 chapter 18 lcd controller driver bit 1 bit 0 fp1, fp0: frame cycle selection bits these bits select the frame cycle of the lcd display (for duty driving) from four types. note: set the register after calculating the optimum frame frequency in accordance with the lcd module used. the frame cycle is affected by the oscillation frequency. table 18.4-1 functions of each bit in lcdc control register 1 (lcr1) (continued) bit name function
469 18.4 registers of the lcd controller driver 18.4.2 lcdc control register 2 (lcr2) the lcdc control register 2 (lcr2) selects whether port 6 is used as segment output pins or as a general-purpose i/o port. n lcdc control register 2 (lcr2) figure 18.4-3 lcdc control register 2 (lcr2) seg12 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address x000000x b initial value seg11 seg9 seg8 seg10 r/w r/w r/w - - seg13 r/w r/w r/w seg12 seg12 selection bit general-purpose i/o port (p64) segment output (seg12) 0 1 seg8 seg8 selection bit general-purpose i/o port (p60) segment output (seg8) 0 1 seg9 seg9 selection bit general-purpose i/o port (p61) segment output (seg9) 0 1 seg10 seg10 selection bit general-purpose i/o port (p62) segment output (seg10) 0 1 seg11 seg11 selection bit general-purpose i/o port (p63) segment output (seg11) 0 1 seg13 seg13 selection bit general-purpose i/o port (p65) segment output (seg13) 0 1 h r/w : read/write enabled x : undefined : initial value
470 chapter 18 lcd controller driver table 18.4-2 functions of each bit in lcdc control register 2 (lcr2) bit name function bit 7 unused bit ? the read value is undefined. ? writing has no effect on operation. bit 6 seg13 seg13 selection bit when this bit is "1," p65 functions as segment output (seg13). when this bit is "0," it functions as a general- purpose i/o port (p65). bit 5 seg12 seg12 selection bit when this bit is "1," p64 functions as segment output (seg12). when this bit is "0," it functions as a general- purpose i/o port (p64). bit 4 seg11 seg11 selection bit when this bit is "1," p63 functions as segment output (seg11). when this bit is "0," it functions as a general- purpose i/o port (p63). bit 3 seg10 seg10 selection bit when this bit is "1," p62 functions as segment output (seg10). when this bit is "0," it functions as a general- purpose i/o port (p62). bit 2 seg9 seg9 selection bit when this bit is "1," p61 functions as segment output (seg9). when this bit is "0," it functions as a general- purpose i/o port (p61). bit 1 seg8 seg8 selection bit when this bit is "1," p60 functions as segment output (seg8). when this bit is "0," it functions as a general- purpose i/o port (p60). bit 0 unused bit ? the read value is undefined. ? writing has no effect on operation.
471 18.4 registers of the lcd controller driver 18.4.3 lcdc control register 3 (lcr3) the lcdc control register 3 (lcr3) selects whether port a is used as segment output pins or as a general-purpose i/o port. n lcdc control register 3 (lcr3) figure 18.4-4 lcdc control register 3 (lcr3) seg05 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 6 h address 00000000 b initial value seg04 seg02 seg01 seg03 r/w r/w r/w seg07 r/w r/w r/w seg04 seg4 selection bit segment output (seg04) general-purpose i/o port (pa4) 0 1 seg00 seg0 selection bit segment output (seg00) general-purpose i/o port (pa0) 0 1 seg01 seg1 selection bit segment output (seg01) general-purpose i/o port (pa1) 0 1 seg02 seg2 selection bit segment output (seg02) general-purpose i/o port (pa2) 0 1 seg03 seg3 selection bit segment output (seg03) general-purpose i/o port (pa3) 0 1 seg05 seg5 selection bit segment output (seg05) general-purpose i/o port (pa5) 0 1 seg06 seg00 r/w r/w seg06 seg6 selection bit segment output (seg06) general-purpose i/o port (pa6) 0 1 seg07 seg7 selection bit segment output (seg07) general-purpose i/o port (pa7) 0 1 r/w : read/write enabled : initial value
472 chapter 18 lcd controller driver table 18.4-3 functions of each bit in lcdc control register 3 (lcr3) bit name function bit 7 seg7 seg7 selection bit when this bit is "0," pa7 functions as segment output (seg07). when this bit is "1," it functions as a general- purpose i/o port (pa7). bit 6 seg6 seg6 selection bit when this bit is "0," pa6 functions as segment output (seg06). when this bit is "1," it functions as a general- purpose i/o port (pa6). bit 5 seg5 seg5 selection bit when this bit is "0," pa5 functions as segment output (seg05). when this bit is "1," it functions as a general- purpose i/o port (pa5). bit 4 seg4 seg4 selection bit when this bit is "0," pa4 functions as segment output (seg04). when this bit is "1," it functions as a general- purpose i/o port (pa4). bit 3 seg3 seg3 selection bit when this bit is "0," pa3 functions as segment output (seg03). when this bit is "1," it functions as a general- purpose i/o port (pa3). bit 2 seg2 seg2 selection bit when this bit is "0," pa2 functions as segment output (seg02). when this bit is "1," it functions as a general- purpose i/o port (pa2). bit 1 seg1 seg1 selection bit when this bit is "0," pa1 functions as segment output (seg01). when this bit is "1," it functions as a general- purpose i/o port (pa1). bit 0 seg0 seg0 selection bit when this bit is "0," pa0 functions as segment output (seg00). when this bit is "1," it functions as a general- purpose i/o port (pa0).
473 18.4 registers of the lcd controller driver 18.4.4 lcdc control register 4 (lcr4) the lcdc control register 4 (lcr4) selects whether port b is used as common output pins or as a general-purpose i/o port. n lcdc control register 4 (lcr4) figure 18.4-5 lcdc control register 4 (lcr4) com2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 8 h address 0000xxxx b initial value com1 com0 r/w r/w r/w - com3 r/w com0 com0 selection bit common output (com0) general-purpose i/o port (pb4) 0 1 com1 com1 selection bit common output (com1) general-purpose i/o port (pb5) 0 1 com2 com2 selection bit common output (com2) general-purpose i/o port (pb6) 0 1 com3 com3 selection bit common output (com3) general-purpose i/o port (pb7) 0 1 - - - r/w : read/write enabled : initial value
474 chapter 18 lcd controller driver table 18.4-4 functions of each bit in lcdc control register 4 (lcr4) bit name function bit 7 com3 com3 selection bit when this bit is "0," pb7 functions as common output (com3). when this bit is "1," it functions as a general- purpose i/o port (pb7). bit 6 com2 com2 selection bit when this bit is "0," pb6 functions as common output (com2). when this bit is "1," it functions as a general- purpose i/o port (pb6). bit 5 com1 com1 selection bit when this bit is "0," pb5 functions as common output (com1). when this bit is "1," it functions as a general- purpose i/o port (pb5). bit 4 com0 com0 selection bit when this bit is "0," pb4 functions as common output (com0). when this bit is "1," it functions as a general- purpose i/o port (pb4). bit 3 bit 2 bit 1 bit 0 unused bits ? the read value is undefined. ? writing has no effect on operation.
475 18.5 lcd display ram in the lcd controller driver 18.5 lcd display ram in the lcd controller driver the lcd display ram is 14 x 4 bit (7 byte) display data memory for generating segment output signals. n lcd display ram and output pins the description in this ram is read automatically in synch with the selection timing of the common signal and output from the segment output pins. if the description in each bit is "1," it is output after being converted into the selected voltage (lcd is displayed). if the description in each bit is "0," it is output after being converted into the non-selected voltage (lcd is not displayed). since the lcd display operation is performed independently of the cpu operation, the lcd display ram can be read and written in any timing. of the seg8 to seg15 pins, the pins not specified as segment output are used as an i/o port (general-purpose output) and the corresponding ram can be used as an ordinary ram. table 18.5-1 "relationships between duty and common output and the bits used in the lcd display ram" shows the relationships between duty and common output and the bits used in the lcd display ram. figure 18.5-1 "assignment of the lcd display ram and the common/ segment output pins" shows the assignment of the lcd display ram and the common/ segment output pins. figure 18.5-1 assignment of the lcd display ram and the common/segment output pins bit3 bit7 bit3 bit7 bit3 bit7 bit3 bit7 bit3 bit7 bit3 bit7 address bit2 bit6 bit2 bit6 bit2 bit6 bit2 bit6 bit2 bit6 bit2 bit6 bit1 bit5 bit1 bit5 bit1 bit5 bit1 bit5 bit1 bit5 bit1 bit5 bit0 bit4 bit0 bit4 bit0 bit4 bit0 bit4 bit0 bit4 bit0 bit4 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 0060 h 0061 h 0063 h 0064 h 0065 h 0066 h area and common pins used at 1/2 duty area and common pins used at 1/3 duty area and common pins used at 1/4 duty com3 com2 com1 com0 0062 h bit3 bit7 bit2 bit6 bit1 bit5 bit0 bit4
476 chapter 18 lcd controller driver table 18.5-1 relationships between duty and common output and the bits used in the lcd display ram duty set value common output used bits of data for display used bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1/2 com0 to com1 (2 pins) - - yes yes - - yes yes 1/3 com0 to com2 (3 pins) - yes yes yes - yes yes yes 1/4 com0 to com3 (4 pins) yes yes yes yes yes yes yes yes yes: used -: not used
477 18.6 operation of the lcd controller driver 18.6 operation of the lcd controller driver the lcd controller driver performs the control and driving required to display the lcd. n explanation of lcd controller driver operation to display the lcd, the settings in figure 18.6-1 "lcd controller driver settings" are required. figure 18.6-1 lcd controller driver settings when the above settings are made and the selected frame cycle generating clock is oscillating, the driving waveform of the lcd panel is output to the common and segment output pins (com0 to com3, seg0 to seg13) in accordance with the description in the lcd display ram and lcrs 1 to 4. even during lcd display operation, the frame cycle generating clock can be switched. however, the display may blink at the time of switching. stop the display temporarily by blanking (lcr1: bk = 1) before switching the clock. the output for driving the display is two-frame alternating current waveform selected by the setting of bias and duty. when lcd display operation is stopped (lcr: ms1, ms0 = 00b), both the common and segment output pins are set at the "l" level. note: when the selected frame cycle oscillating clock is stopped during lcd display operation, a dc voltage is applied to the lcd elements because the alternating current generating circuit is stopped. in this case, the lcd display operation must be stopped in advance. the conditions for stopping the main clock (time base timer) and subclock are dependent on the selection of the clock mode and standby mode. when the timer base timer output is selected (lcr1: css = 0), clearing the time base timer affects the frame cycle. : used bit 0 : 0 is set lcd display ram 060 h to 066 h display data bk bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lcr1 ms1 fp1 fp0 ms0 css vsel seg12 lcr2 seg11 seg9 seg8 seg10 - seg13 lcden 0 other than 00 seg04 lcr3 seg03 seg01 seg00 seg02 seg05 com2 lcr4 com1 com0 - - com3 - seg06 seg07 - -
478 chapter 18 lcd controller driver n lcd driving waveform driving the lcd with direct current creates a chemical reaction that degrades the lcd display elements. therefore, the lcd controller driver contains an alternating current generating circuit and drives the lcd with the two frame alternating current waveform. the three types of output waveforms are as follows. ? 1/2 bias, 1/2 duty output waveform ? 1/3 bias, 1/3 duty output waveform ? 1/3 bias, 1/4 duty output waveform
479 18.6 operation of the lcd controller driver 18.6.1 output waveforms during lcd controller driver operation (1/2 duty) the display driving output uses two-frame alternating current waveforms in the multiplex driving method. in 1/2 duty, only com0 and com1 are used for display. com2 and com3 are not used. n example of 1/2 bias, 1/2 duty output waveforms for display, the lcd elements with the maximum potential difference between the common output and the segment output are turned on. figure 18.6-2 "example of 1/2 bias, 1/2 duty output waveform" shows the output waveforms when the description in the lcd display ram is as shown in table 18.6-1 "description example of lcd display ram". table 18.6-1 description example of lcd display ram segment description in lcd display ram com3 com2 com1 dom0 seg m CC00 seg m+1 CC01
480 chapter 18 lcd controller driver figure 18.6-2 example of 1/2 bias, 1/2 duty output waveform v3 v2=v1 v0=vss v3(on) v2 vss -v2 -v3(on) v3(on) v2 vss -v2 -v3(on) v3(on) v2 vss -v2 -v3(on) v3(on) v2 vss -v2 -v3(on) v3 v2=v1 v0=vss v3 v2=v1 v0=vss v3 v2=v1 v0=vs0 v3 v2=v1 v0=vss v3 v2=v1 v0=vss com0 com1 com2 com3 segn segn+1 voltage difference between com0 and segn voltage difference between com1 and segn voltage difference between com0 and segn+1 voltage difference between com1 and segn+1 1 frame v0 to v3: voltages at v0 to v3 pins 1 cycle
481 18.6 operation of the lcd controller driver n lcd panel connection example and display data example (1/2 duty driving method) figure 18.6-3 connection example of segment and common pins and correspondence with display data com1 com0 *1 to *7: indicates relationships with the lcd display ram. bits 2, 3, 6, and 7 are not used. com1 1 1 1 0 com0 1 0 0 1 seg0 seg1 seg2 seg3 060 h 061 h address 0 : off 1 : on com3 bit3 bit7 bit3 bit7 com2 bit2 bit6 bit2 bit6 n h n+1 h address example: when the number "5" is displayed. segn [address] [segment no.] seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 060 h 061 h 062 h 063 h 064 h 065 h com1 0 1 1 1 0 0 1 1 1 1 0 1 com0 1 1 1 1 0 0 1 0 0 1 1 1 [lcd display ram] [lcd panel] data relationships example from 0 to 9 lcd display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 *1 *1 *3 *3 *5 *5 *7 *7 *0 *0 *2 *2 *4 *4 *6 *6 bit1 bit5 bit1 bit5 bit0 bit4 bit0 bit4 segn segn+1 segn+1 segn+2 segn+2 segn+3 segn+3 com2 com3 com2 com3 com0 com1
482 chapter 18 lcd controller driver 18.6.2 output waveforms during lcd controller driver operation (1/3 duty) in 1/3 duty, only com0, com1, and com2 are used for display. com3 is not used. n example of 1/3 bias, 1/3 duty output waveforms for display, the lcd elements with the maximum potential difference between the common output and the segment output are turned on. figure 18.6-4 "example of 1/3 bias, 1/3 duty output waveforms" shows the output waveforms when the description in the lcd display ram is as shown in table 18.6-2 "description example of lcd display ram". table 18.6-2 description example of lcd display ram segment description in lcd display ram com3 com2 com1 dom0 seg m -100 seg m+1 -101 -: not used
483 18.6 operation of the lcd controller driver figure 18.6-4 example of 1/3 bias, 1/3 duty output waveforms v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) com0 com1 com2 com3 segn segn+1 1 frame 1 cycle v0 to v3: voltages at v0 to v3 pins voltage difference between com1 and segn voltage difference between com2 and segn voltage difference between com0 and segn+1 voltage difference between com2 and segn+1 voltage difference between com1 and segn+1 voltage difference between com0 and segn
484 chapter 18 lcd controller driver n lcd panel connection example and display data example (1/3 duty driving method) figure 18.6-5 connection example of segment and common pins and relationships to display data com0 com2 com1 segn *0 to *8: indicates relationships with the lcd display ram. bits 3 and 7 and *2 are not used. com2 0 1 0 0 1 0 com1 0 1 1 0 1 1 com0 1 1 0 1 1 0 seg0 seg1 seg2 seg3 seg4 seg5 when starting with bit 0 when starting with bit 4 060 h 061 h 062 h address 0 : off 1 : on com3 bit3 bit7 bit3 n h n+1 h address example: when the number "5" is displayed. [address] [segment no.] seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 060 h 061 h 062 h 063 h 064 h com0 1 1 1 0 0 1 0 1 1 com1 1 0 1 0 0 1 1 1 0 com2 0 1 1 0 0 1 0 1 1 data relationships example from 0 to 9 since 1/3 duty displays two digits in three bytes, there are two types of data in data arrangement: the first byte data starting with bit 0 and the second byte data starting with bit 4. lcd display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 : data when starting with bit 4 : data when starting with bit 0 [lcd display ram] [lcd panel] *1 *1 *3 *3 *5 *5 *8 *8 *7 *7 *0 *0 *2 *4 *4 *6 *6 bit1 bit5 bit1 bit2 bit6 bit2 bit0 bit4 bit0 segn segn+1 segn+1 segn+2 segn+2 segn+3 com0 com1 com2 com3 com3
485 18.6 operation of the lcd controller driver 18.6.3 output waveforms during lcd controller driver operation (1/4 duty) in 1/4 duty, all of com0, com1, com2 and com3 are used for display. n example of 1/3 bias, 1/4 duty output waveforms for display, the lcd elements with the maximum potential difference between the common output and the segment output are turned on. figure 18.6-6 "example of 1/3 bias, 1/4 duty output waveforms" shows the output waveforms when the description in the lcd display ram is as shown in table 18.6-3 "description example of lcd display ram". table 18.6-3 description example of lcd display ram segment description in lcd display ram com3 com2 com1 dom0 seg m 0100 seg m+1 0101
486 chapter 18 lcd controller driver figure 18.6-6 example of 1/3 bias, 1/4 duty output waveforms v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss v3 v2 v1 v0=vss com0 com1 com2 com3 segn segn+1 1 frame 1 cycle v0 to v3: voltages at v0 to v3 pins v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) voltage difference between com1 and segn voltage difference between com2 and segn voltage difference between com1 and segn+1 voltage difference between com3 and segn+1 voltage difference between com2 and segn+1 voltage difference between com0 and segn v3(on) v2 v1 vss -v1 -v2 -v3(on) v3(on) v2 v1 vss -v1 -v2 -v3(on) voltage difference between com3 and segn voltage difference between com0 and segn+1
487 18.6 operation of the lcd controller driver n connection example of 8-segment lcd panel and display data example (1/4 duty driving method) figure 18.6-7 connection example of segment and common pins and relationships to display data com0 com2 com1 segn segn+1 *2 *1 *0 *3 *7 *6 *4 *5 *0 to *7: indicates relationships with the lcd display ram. com3 1 0 com2 1 0 com1 0 1 com0 1 1 seg0 seg1 060 h segn segn+1 n h com3 com0 1 1 0 0 0 1 0 1 com1 1 0 0 0 1 1 0 1 com2 1 1 0 1 1 1 1 1 com3 1 1 1 1 0 1 1 1 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 060 h 061 h 062 h 063 h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 address address example: when the number "5" is displayed. 0 : off 1 : on data relationships example from 0 to 9 lcd display [address] [segment no.] [lcd display ram] [lcd panel]
488 chapter 18 lcd controller driver
489 chapter 19 wild register function this chapter describes the functions and operations of the wild register function. 19.1 "overview of the wild register function" 19.2 "configuration of the wild register function" 19.3 "registers of the wild register function" 19.4 "operation of the wild register function"
490 chapter 19 wild register function 19.1 overview of the wild register function the wild register function applies a patch for a program fault by setting an address and correction data in an internal register. up to six bytes of data can be corrected. n wild register function the wild register function assigns an address in the rom space of the microcontroller and replaces the existing data at the address with new data. thus, if a program has a fault, you can correct the faulty data by setting its address and the address if the correction data in the register. n wild register application address the address space where the wild register function can be used depends on the model. table 19.1-1 "applicable addresses for the wild register function" shows the applicable addresses for the wild register function for each model. table 19.1-1 applicable addresses for the wild register function model name rom space mb89pv570 0c92 h to ffff h mb89p579 1000 h to ffff h MB89577 8000 h to ffff h
491 19.2 configuration of the wild register function 19.2 configuration of the wild register function the wild register function consists of the following two blocks: ? memory area section data setting register (wrdr) upper address setting register (wrarh) lower address setting register (wrarl) ? control circuit section address comparison enable register (wren) n block diagram of the wild register function figure 19.2-1 block diagram of the wild register function data setting register (wrdr) address setting register (wrarh) address setting register (wrarl) memory area section access control circuit address comparison en register(wren) address comparison access control control circuit section internal data bus address bus decoder internal rom/ram wild register function matching signal
492 chapter 19 wild register function m memory area section the memory area section consists of the data setting registers, the address setting register (h address), and the address setting register (l address). in the memory area section, set the address and the data that will be used to replace the fault using the wild register function. each mb89570 series model has these registers, each of which is six bytes. m control circuit section the control circuit section compares the data set in the address setting registers and the actual data on the address bus. if it finds a match, it sets the data in the data setting register on the data bus. the operation of the control circuit section is controlled by the address comparison enable register.
493 19.3 registers of the wild register function 19.3 registers of the wild register function this section describes the registers related to the wild register function. n registers related to the wild register function figure 19.3-1 registers related to the wild register function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 c 8 2 h 0 c 8 5 h 0 c 8 8 h 0 c 8 b h 0 c 8 e h 0 c 9 1 h address xxxxxxxx b initial value w wrdr0 to wrdr5 [data setting registers] wwwwwww rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 c 8 0 h 0 c 8 3 h 0 c 8 6 h 0 c 8 9 h 0 c 8 c h 0 c 8 f h address initial value r/w wrarh0 to wrarh5 [address setting registers (upper bytes)] r/w r/w r/w r/w r/w r/w r/w ra14 ra13 ra12 ra11 ra10 ra09 ra08 ra15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 c 8 1 h 0 c 8 4 h 0 c 8 7 h 0 c 8 a h 0 c 8 d h 0 c 9 0 h address initial value r/w wrarl0 to wrarl5 [address setting registers (lower bytes)] r/w r/w r/w r/w r/w r/w r/w ra06 ra05 ra04 ra03 ra02 ra01 ra00 ra07 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xx000000 b initial value wren [address comparison enable register] r/w r/w r/w r/w r/w r/w - en05 en04 en03 en02 en01 en00 - address 0 0 7 7 h xxxxxxxx b xxxxxxxx b r/w : read/write enabled w : write only x : undefined
494 chapter 19 wild register function 19.3.1 data setting registers (wrdr0 to 5) the data setting registers (wrdr0 to 5) contain correction data to be set using the wild register function. n data setting registers (wrdr) figure 19.3-2 data setting registers (wrdr) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wrdr0 0 c 8 2 h address xxxxxxxx b initial value wwwwwwww rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 xxxxxxxx b wwwwwwww rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 wrdr1 0 c 8 5 h wrdr2 0 c 8 8 h wrdr3 0 c 8 b h wrdr4 0 c 8 e h wrdr5 0 c 9 1 h xxxxxxxx b wwwwwwww rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 xxxxxxxx b wwwwwwww rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 xxxxxxxx b wwwwwwww rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 xxxxxxxx b wwwwwwww rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd07 w : write only x : undefined
495 19.3 registers of the wild register function note: while the wren register is set, reading the address set in wrah (address h) and wral (address l) reads the value in the wrdr (data) register. table 19.3-1 functions of the data setting registers (wrdr) wild register number register name function 0 wrdr0 one-byte register that stores data at the address assigned by wrarl and wrarh. this data is valid at the address (wrarl and wrarh) corresponding to each wild register number. 1 wrdr1 2 wrdr2 3 wrdr3 4 wrdr4 5 wrdr5
496 chapter 19 wild register function 19.3.2 upper address setting registers (wrarh0 to 5) the upper address setting registers (wrarh0 to 5) contain the upper part of an address where data is corrected. n upper address setting registers (wrarh) figure 19.3-3 upper address setting registers (wrarh) wrarh0 0 c 8 0 h address wrarh1 0 c 8 3 h wrarh2 0 c 8 6 h wrarh3 0 c 8 9 h wrarh4 0 c 8 c h wrarh5 0 c 8 f h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value r/w r/w r/w r/w r/w r/w r/w r/w ra14 ra13 ra12 ra11 ra10 ra09 ra08 ra15 r/w r/w r/w r/w r/w r/w r/w r/w ra14 ra13 ra12 ra11 ra10 ra09 ra08 ra15 r/w r/w r/w r/w r/w r/w r/w r/w ra14 ra13 ra12 ra11 ra10 ra09 ra08 ra15 r/w r/w r/w r/w r/w r/w r/w r/w ra14 ra13 ra12 ra11 ra10 ra09 ra08 ra15 r/w r/w r/w r/w r/w r/w r/w r/w ra14 ra13 ra12 ra11 ra10 ra09 ra08 ra15 r/w r/w r/w r/w r/w r/w r/w r/w ra14 ra13 ra12 ra11 ra10 ra09 ra08 ra15 xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b r/w : read/write enabled x : undefined
497 19.3 registers of the wild register function table 19.3-2 functions of the upper address setting registers (wrarh) wild register number register name function 0 wrarh0 one-byte register that specifies the upper address of memory to be assigned. specifies an address corresponding to the wild register number. 1 wrarh1 2 wrarh2 3 wrarh3 4 wrarh4 5 wrarh5
498 chapter 19 wild register function 19.3.3 lower address setting registers (wrarl 0 to 5) the lower address setting registers (wrarl0 to 5) contain the lower part of an address where data is corrected. n lower address setting registers (wrarl) figure 19.3-4 lower address setting registers (wrarl) wrarl0 0 c 8 1 h address wrarl1 0 c 8 4 h wrarl2 0 c 8 7 h wrarl3 0 c 8 a h wrarl4 0 c 8 d h wrarl5 0 c 9 0 h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value r/w r/w r/w r/w r/w r/w r/w r/w ra06 ra05 ra04 ra03 ra02 ra01 ra00 ra07 r/w r/w r/w r/w r/w r/w r/w r/w ra06 ra05 ra04 ra03 ra02 ra01 ra00 ra07 r/w r/w r/w r/w r/w r/w r/w r/w ra06 ra05 ra04 ra03 ra02 ra01 ra00 ra07 r/w r/w r/w r/w r/w r/w r/w r/w ra06 ra05 ra04 ra03 ra02 ra01 ra00 ra07 r/w r/w r/w r/w r/w r/w r/w r/w ra06 ra05 ra04 ra03 ra02 ra01 ra00 ra07 r/w r/w r/w r/w r/w r/w r/w r/w ra06 ra05 ra04 ra03 ra02 ra01 ra00 ra07 xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b r/w : read/write enabled x : undefined
499 19.3 registers of the wild register function table 19.3-3 functions of the upper address setting registers (wrarh) wild register number register name function 0 wrarl0 one-byte register that specifies the lower address of memory to be assigned. specifies an address corresponding to a wild register number. 1 wrarl1 2 wrarl2 3 wrarl3 4 wrarl4 5 wrarl5
500 chapter 19 wild register function 19.3.4 address comparison enable register (wren) the address comparison enable register (wren) enables or disables the operation of the wild register function for each wild register number. n address comparison enable register (wren) figure 19.3-5 address comparison enable register (wren) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xx000000 b initial value wren (address comparison enable register) r/w r/w r/w r/w r/w r/w - en05 en04 en03 en02 en01 en00 - address 0 0 7 7 h r/w : read/write enabled x : undefined
501 19.3 registers of the wild register function table 19.3-4 functions of the address comparison enable register (wren) bit name function bit 7 bit 6 unused bits ? the read value is undefined. ? for a write, always write 0. bit 5 en05: ? setting this bit to 0 disables the wild register function. ? setting this bit to 1 enables the wild register function. if a match is then found for the address set in wrarh5 and wrarl5, the value in the wrdr5 is output to the internal bus instead of the value in rom. bit 4 en04: ? setting this bit to 0 disables the wild register function. ? setting this bit to 1 enables the wild register function. if a match is then found for the address set in wrarh4 and wrarl4, the value in the wrdr4 is output to the internal bus instead of the value in rom. bit 3 en03: ? setting this bit to 0 disables the wild register function. ? setting this bit to 1 enables the wild register function. if a match is then found for the address set in wrarh3 and wrarl3, the value in wrdr3 is output to the internal bus instead of the value in rom. bit 2 en02: ? setting this bit to 0 disables the wild register function. ? setting this bit to 1 enables the wild register function. if a match is then found for the address set in wrarh2 and wrarl2, the value in the wrdr2 is output to the internal bus instead of the value in rom. bit 1 en01: ? setting this bit to 0 disables the wild register function. ? setting this bit to 1 enables the wild register function. if a match is then found for the address set in wrarh1 and wrarl1, the value in the wrdr1 is output to the internal bus instead of the value in rom. bit 0 en00: ? setting this bit to 0 disables the wild register function. ? setting this bit to 1 enables the wild register function. if a match is then found for the address set in wrarh0 and wrarl0, the value in the wrdr0 is output to the internal bus instead of the value in rom.
502 chapter 19 wild register function 19.4 operation of the wild register function this section describes the sequence of wild register function operations. n sequence of wild register function operations the following shows the sequence of wild register function operations. in the operation example, the data ff h at the address fc36 h is corrected to b5 h . n list of wild register addresses the following shows the list of addresses corresponding to the wild register numbers. table 19.4-1 sequence of wild register function operations operation operation example 1 set the address of the wild register support area in the address setting registers. address: fc36 h , data: ff h wrarl0=36 h wrarh0=fc h 2 set the correction data in the data setting registers. wrdr0=b5 h 3 set 1 in the address comparison enable register. wren=01 h 4 if the addresses match, the wild register function is enabled. if the address fc36 h is accessed data = b5 h table 19.4-2 list of wild register addresses upper address lower address data register name address register name address register name address 1 wrarh1 0c80 h wrarl1 0c81 h wrdr1 0c82 h 2 wrarh2 0c83 h wrarl2 0c84 h wrdr2 0c85 h 3 wrarh3 0c86 h wrarl3 0c87 h wrdr3 0c88 h 4 wrarh4 0c89 h wrarl4 0c8a h wrdr4 0c8b h 5 wrarh5 0c8c h wrarl5 0c8d h wrdr5 0c8e h 6 wrarh6 0c8f h wrarl6 0c90 h wrdr6 0c91 h
503 appendix this appendix includes i/o maps, instruction lists, and other information. appendix a "i/o maps" appendix b "overview of instructions" appendix c "mask options" appendix d "one-time prom and eprom microcontroller write specification" appendix e "pin statuses of the mb89570 series"
504 appendix a i/o maps appendix a i/o maps the addresses shown in table a-1 "i/o map" are assigned to the registers of peripheral functions contained in the mb89570 series. n i/o maps table a-1 i/o map address abbreviation of register register name read and write initial value 00 h pdr0 port 0 data register r/w xxxxxxxx b 01 h ddr0 port 0 direction register w 00000000 b 02 h pdr1 port 1 data register r/w xxxxxxxx b 03 h ddr1 port 1 direction register w 00000000 b 04 h pdr2 port 2 data register r/w xxxxxxxx b 05 h (unused area) 06 h ddr2 port 2 direction register r/w 00000000 b 07 h sycc system clock control register r/w xxxmm100 b 08 h stbc standby control register r/w 00010xxx b 09 h wdtc watchdog control register r/w 0xxxxxxx b 0a h tbtc timebase timer control register r/w x0xxx000 b 0b h wpcr watch prescaler control register r/w x0xx0000 b 0c h (unused area) 0d h (unused area) 0e h rsfr reset flag register r xxxxxxxx b 0f h (unused area) 10 h smc1 serial mode control register 1 r/w 00000000 b 11 h smm2 serial mode control register 2 r/w 00000000 b 12 h ssd serial status and data register r 00001xxx b 13 h sidr/sodr serial input/serial output data register r/w xxxxxxxx b 14 h src baud rate generator reload register r/w xxxxxxxx b 15 h pdra port a data register r/w 11111111 b 16 h lcr3 lcdc control register 3 r/w 00000000 b
505 appendix a i/o maps 17 h pdrb port b data register r/w 11111111 b 18 h lcr4 lcdc control register 4 r/w 0000xxxx b 19 h brsr3 bridge circuit selection register 3 r/w xxxxx001 b 1a h t2cr timer 2 control register r/w x00000x0 b 1b h t1cr timer 1 control register r/w x00000x0 b 1c h t2dr timer 2 data register r/w xxxxxxxx b 1d h t1dr timer 1 data register r/w xxxxxxxx b 1e h (unused area) 1f h (unused area) 20 h pdr3 port 3 data register r/w xx111111 b 21 h pdr4 port 4 data register r/w xxxx1111 b 22 h pdr5 port 5 data register r/w xxxxxxxx b 23 h ddr5 port 5 direction register r/w x0000000 b 24 h pdr6 port 6 data register r/w xx111111 b 25 h pdr7 port 7 data register r/w xxxxxxxx b 26 h ddr7 port 7 direction register r/w 00000000 b 27 h pdr8 port 8 data register r/w xxxxxxxx b 28 h ddr8 port 8 direction register r/w 000x0000 b 29 h pdr9 port 9 data register r/w xxxxxxxx b 2a h ddr9 port 9 direction register r/w xxxxx000 b 2b h (unused area) 2c h (unused area) 2d h aden1 a/d enable register 1 r/w xxxx1111 b 2e h aden2 a/d enable register 2 r/w 11111111 b 2f h adc1 a/d control register 1 r/w 00000000 b 30 h adc2 a/d control register 2 r/w x000001 b 31 h (unused area) 32 h addh a/d data register (upper bytes) r/w xxxxxxxx b 33 h addl a/d data register (lower bytes) r/w xxxxxxxx b 34 h (unused area) 35 h ibsr i 2 c bus status register r 00000000 b table a-1 i/o map (continued) address abbreviation of register register name read and write initial value
506 appendix a i/o maps 36 h ibcr i 2 c bus control register r/w 00000000 b 37 h iccr i 2 c clock control register r/w 0x0xxxxx b 38 h iadr i 2 c address register r/w xxxxxxxx b 39 h idar i 2 c data register r/w xxxxxxxx b 3a h itcr i 2 c timeout control register r/w x0000000 b 3b h itsr i 2 c timeout status register r/w xxxx0000 b 3c h itod i 2 c timeout data register r/w xxxxxxxx b 3d h itoc i 2 c timeout clock register r/w xxxxxxxx b 3e h imto i 2 c master timeout register r/w xxxxxxxx b 3f h isto i 2 c slave timeout register r/w xxxxxxxx b 40 h mbsr multi-address i 2 c bus status register r 00000000 b 41 h mbcr multi-address i 2 c bus control register r/w 00000000 b 42 h mccr multi-address i 2 c bus clock control register r/w 0x0xxxxx b 43 h madr1 multi-address i 2 c bus address register 1 r/w xxxxxxxx b 44 h madr2 multi-address i 2 c bus address register 2 r/w xxxxxxxx b 45 h madr3 multi-address i 2 c bus address register 3 r/w xxxxxxxx b 46 h madr4 multi-address i 2 c bus address register 4 r/w xxxxxxxx b 47 h madr5 multi-address i 2 c bus address register 5 r/w xxxxxxxx b 48 h madr6 multi-address i 2 c bus address register 6 r/w xxxxxxxx b 49 h madr multi-address i 2 c bus data register r/w xxxxxxxx b 4a h mtcr multi-address i 2 c bus timeout control register r/w x0000000 b 4b h mtsr multi-address i 2 c bus timeout status register r/w xxxx0000 b 4c h mtod multi-address i 2 c bus timeout data register r/w xxxxxxxx b 4d h mtoc multi-address i 2 c bus timeout clock register r/w xxxxxxxx b 4e h mmto multi-address i 2 c bus master timeout register r/w xxxxxxxx b 4f h msto multi-address i 2 c bus slave timeout register r/w xxxxxxxx b 50 h malr multi-address i 2 c bus alart register r/w xxxx0000 b 51 h cocr1 comparator control register 1 r/w xx000000 b 52 h cocr2 comparator control register 2 r/w xxx11111 b 53 h cosr1 comparator status register 1 r/w 00000000 b table a-1 i/o map (continued) address abbreviation of register register name read and write initial value
507 appendix a i/o maps 54 h cicr1 comparator interrupt control register 1 r/w 00000000 b 55 h cosr2 comparator status register 2 r/w xx000000 b 56 h cicr2 comparator interrupt control register 2 r/w xx000000 b 57 h cosr3 comparator status register 3 r xxxxxxxx b 58 h cosr4 comparator status register 4 r xxxxxxxx b 59 h cier comparator input enable register r/w xxx11111 b 5a h eic1 external interrupt control register 1 r/w 00000000 b 5b h eic2 external interrupt control register 2 r/w 00000000 b 5c h brsr1 bridge circuit selection register 1 r/w xxxxx000 b 5d h brsr2 bridge circuit selection register 2 r/w xx000000 b 5e h lcr1 lcdc control register 1 r/w 00010000 b 5f h lcr2 lcdc control register 2 r/w x000000x b 60 h to 66 h vram lcd display ram r/w xxxxxxxx b 67 h to 6f h (unused area) 70 h dacr d/a control register r/w xxxxxx00 b 71 h dadr1 d/a data register 1 r/w xxxxxxxx b 72 h dadr2 d/a data register 2 r/w xxxxxxxx b 73 h tmcr timer control register r/w xx000000 b 74 h tchr timer count register (upper bytes) r/w 00000000 b 75 h tclr timer count register (lower bytes) r/w 00000000 b 76 h (unused area) 77 h wren wild register address comparison enable register r/w xx000000 b 78 h wild register test register 79 h (unused area) 7a h (unused area) 7b h ilr1 interrupt level setting register 1 w 11111111 b 7c h ilr2 interrupt level setting register 2 w 11111111 b 7d h ilr3 interrupt level setting register 3 w 11111111 b table a-1 i/o map (continued) address abbreviation of register register name read and write initial value
508 appendix a i/o maps m description of "read and write" ? r/w: read/write enabled ? r: read only 7e h ilr4 interrupt level setting register 4 w 11111111 b 7f h (unused area) 0c80 h wrarh1 wild register address setting register 1 (upper bytes) r/w xxxxxxxx 0c81 h wrarl1 wild register address setting register 1 (lower bytes) r/w xxxxxxxx 0c82 h wrdr1 wild register data setting register 1 w xxxxxxxx 0c83 h wrarh2 wild register address setting register 2 (upper bytes) r/w xxxxxxxx 0c84 h wrarl2 wild register address setting register 2 (lower bytes) r/w xxxxxxxx 0c85 h wrdr2 wild register data setting register 2 w xxxxxxxx 0c86 h wrarh3 wild register address setting register 3 (upper bytes) r/w xxxxxxxx 0c87 h wrarl3 wild register address setting register 3 (lower bytes) r/w xxxxxxxx 0c88 h wrdr3 wild register data setting register 3 w xxxxxxxx 0c89 h wrarh4 wild register address setting register 4 (upper bytes) r/w xxxxxxxx 0c8a h wrarl4 wild register address setting register 4 (lower bytes) r/w xxxxxxxx 0c8b h wrdr4 wild register data setting register 4 w xxxxxxxx 0c8c h wrarh5 wild register address setting register 5 (upper bytes) r/w xxxxxxxx 0c8d h wrarl5 wild register address setting register 5 (lower bytes) r/w xxxxxxxx 0c8e h wrdr5 wild register data setting register 5 w xxxxxxxx 0c8f h wrarh6 wild register address setting register 6 (upper bytes) r/w xxxxxxxx 0c90 h wrarl6 wild register address setting register 6 (lower bytes) r/w xxxxxxxx 0c91 h wrdr6 wild register data setting register 6 w xxxxxxxx table a-1 i/o map (continued) address abbreviation of register register name read and write initial value
509 appendix a i/o maps ? w: write only m description of "initial value" ? 0: this bit has the initial value of "0". ? 1: this bit has the initial value of "1". ? x: this bit has an undefined initial value. note: do not use the unused area.
510 appendix b overview of instructions appendix b overview of instructions appendix b describes the instructions used by the f 2 mc-8l. b.1 "overview of f 2 mc-8l instructions" b.2 "addressing" b.3 "special instructions" b.4 "bit manipulation instructions (setb, clrb)" b.5 "f 2 mc-8l instructions" b.6 "instruction map"
511 appendix b overview of instructions b.1 overview of f 2 mc-8l instructions the f 2 mc-8l supports 140 types of instructions. n overview of f2mc-8l instructions the f 2 mc-8l has 140 1-byte machine instructions (256-byte instruction map). an instruction code consists of an instruction and zero or more operands that follow. figure b.1-1 "relationship between the instruction codes and the instruction map" shows the relationship between the instruction codes and the instruction map. figure b.1-1 relationship between the instruction codes and the instruction map ? the instructions are classified into four types: transfer, arithmetic, branch, and other. ? a variety of addressing methods is available. one of ten addressing modes can be selected depending on the selected instruction and specified operand(s). ? bit manipulation instructions are provided. they can be used for read-modify-write operations. ? some instructions are used for special operations. 0 to 2 bytes, which are assigned depending on the instruction 1 byte instruction code machine instruction operand operand higher 4 bits [instruction map] lower 4 bits
512 appendix b overview of instructions n symbols used with instructions table b.1-1 "symbols in the instruction list" lists the symbols used in the instruction code descriptions in appendix b. table b.1-1 symbols in the instruction list symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir:16 bit direct address (8 bits:3 bits) rel branch relative address (8 bits) @ register indirect addressing (examples: @a, @ix, @ep) a accumulator (8 or 16 bits, which are determined depending on the instruction being used) ah higher 8 bits of the accumulator (8 bits) al lower 8 bits of the accumulator (8 bits) t temporary accumulator (8 or 16 bits, which are determined depending on the instruction being used) th higher 8 bits of the temporary accumulator (8 bits) tl lower 8 bits of the temporary accumulator (8 bits) ix index register (16 bits) ep extra pointer (16 bits) pc program counter (16 bits) sp stack pointer (16 bits) ps program status (16 bits) dr either accumulator or index register (16 bits) ccr condition code register (8 bits) rp register bank pointer (5 bits) ri general-purpose register (8 bits, i = 0 to 7) x x is immediate data (8 or 16 bits, which are determined depending on the instruction being used). (x) the content of x is to be accessed (8 or 16 bits, which are determined depending on the instruction being used). ((x)) the address indicated by the x is to be accessed (8 or 16 bits, which are determined depending on the instruction being used).
513 appendix b overview of instructions n items in the instruction list table b.1-2 items in the instruction list item description mnemonic this column shows the instruction in assembly language. to this column shows the number of cycles required by the instruction (instruction cycle count). # this column shows the number of bytes for the instruction. operation this column shows the operation performed by the instruction. tl, th, ah these columns indicate a change in the contents of tl, th, and ah (automatic transfer from a to t) upon the execution of the instruction. the meanings of symbols in each column are as follows: ? "-" indicates that no change is made. ? "dh" indicates the higher 8 bits of data in the operation column. ? "al" and "ah" indicate that the contents of al and ah immediately before the execution of the instruction are set. ? "00" indicates that 00 is set. n, z, v, c these columns indicate whether their respective flags are changed upon the execution of the instruction. a plus (+) sign indicates that the instruction changes the corresponding flag. op code this column shows the operation code(s) of the instruction. when the instruction uses two or more operation codes, the following notation is used: [example] 48 to 4f: this represents from 48 to 4f.
514 appendix b overview of instructions b.2 addressing the f2mc-8l has the following ten addressing modes: ? direct addressing ? extended addressing ? bit direct addressing ? index addressing ? pointer addressing ? general-purpose register addressing ? immediate addressing ? vector addressing ? relative addressing ? inherent addressing n explanation of addressing m direct addressing direct addressing is indicated by dir in the instruction list. this addressing is used to access the area between 0000 h and 00ff h . in this addressing mode, the higher byte of the address is 00 h and the lower byte is specified by the operand. figure b.2-1 "example of direct addressing" shows an example. figure b.2-1 example of direct addressing m extended addressing extended addressing is indicated by ext in the instruction list. this addressing is used to access the entire 64-kb area. in this addressing mode, the first operand specifies the higher byte of the address, and the second operand specifies the lower byte. figure b.2-2 "example of extended addressing" shows an example. figure b.2-2 example of extended addressing m bit direct addressing bit direct addressing is indicated by dir:b in the instruction list. this addressing is used to access a particular bit in the area between 0000 h and 00ff h . in this addressing mode, the mov 12 h , a 4 5 h 4 5 h a 0 0 1 2 h 1 2 3 4 h movw a, 1 2 3 4 h 5 6 7 8 h a 5 6 h 7 8 h 1 2 3 5 h
515 appendix b overview of instructions higher byte of the address is 00 h and the lower byte is specified by the operand. the bit position at the address is specified by the lower three bits of the operation code. figure b.2-3 "example of bit direct addressing" shows an example. figure b.2-3 example of bit direct addressing m index addressing index addressing is indicated by @ix+off in the instruction list. this addressing is used to access the entire 64-kb area. in this addressing mode, the address is the value resulting from sign-extending the contents of the first operand and adding them to ix (index register). figure b.2-4 "example of index addressing" shows an example. figure b.2-4 example of index addressing m pointer addressing pointer addressing is indicated by @ep in the instruction list. this addressing is used to access the entire 64-kb area. in this addressing mode, the address is contained in ep (extra pointer). figure b.2-5 "example of pointer addressing" shows an example. figure b.2-5 example of pointer addressing m general-purpose register addressing general-purpose register addressing is indicated by ri in the instruction list. this addressing is used to access a register bank in the general-purpose register area. in this addressing mode, the higher byte of the address is always 01 and the lower byte is specified based on the contents of rp (register bank pointer) and the lower three bits of the operation code. figure b.2-6 "example of general-purpose register addressing" shows an example. figure b.2-6 example of general-purpose register addressing m immediate addressing immediate addressing is indicated by #d8 in the instruction list. this addressing is used when setb 34 h : 2 xxxxx 1x x b 0 0 3 4 h 7 6 5 4 3 2 1 0 2 7 f f h movw a, @ix+5 a h 1 2 3 4 h a 1 2 h 3 4 h 2 8 0 0 h 2 7 a 5 h ix 2 7 a 5 h movw a, @ep 1 2 3 4 h a 1 2 h 3 4 h 2 7 a 6 h 2 7 a 5 h ep 0 1 5 6 h mov a, r 6 ab h a a b h 0 1 0 1 0 b rp
516 appendix b overview of instructions immediate data is required. in this addressing mode, the operand is used as immediate data. whether the data is specified in bytes or words is determined by the operation code. figure b.2-7 "example of immediate addressing" shows an example. figure b.2-7 example of immediate addressing m vector addressing vector addressing is indicated by vct in the instruction list. this addressing is used to branch to a subroutine address stored in the vector table. in this addressing mode, vct information is contained in the operation codes, and the corresponding table addresses are created as shown in table b.2-1 "vector table addresses corresponding to vct". figure b.2-8 "example of vector addressing" shows an example. figure b.2-8 example of vector addressing m relative addressing relative addressing is indicated by rel in the instruction list. this addressing is used to branch to within the area between the address 128 bytes higher and that 128 bytes lower relative to the address contained in the pc (program counter). in this addressing mode, the result of a signed addition of the contents of the operand to the pc is stored in the pc. figure b.2-9 "example of mov a, #56 h 5 6 h a table b.2-1 vector table addresses corresponding to vct #vct vector table address (higher address:lower address of branch destination) 0ffc0 h : ffc1 h 1ffc2 h : ffc3 h 2ffc4 h : ffc5 h 3ffc6 h : ffc7 h 4ffc8 h : ffc9 h 5 ffca h : ffcb h 6 ffcc h : ffcd h 7 ffce h : ffcf h f f c a h callv #5 f e d c h pc f e h d c h f f c b h (conversion)
517 appendix b overview of instructions relative addressing" shows an example. figure b.2-9 example of relative addressing in this example, a branch to the address of the bne operation code occurs, thus resulting in an infinite loop. m inherent addressing inherent addressing is indicated as the addressing without operands in the instruction list. this addressing is used to perform the operation determined by the operation code. in this addressing mode, different operations are performed via different instructions. figure b.2-10 "example of inherent addressing" shows an example. figure b.2-10 example of inherent addressing 9ab a h bne f eh current pc 9ab c h previous pc 9abc h + fffe h 9 a b d h nop 9 a b c h current pc previous pc
518 appendix b overview of instructions b.3 special instructions this section describes the special instructions used for other than addressing. n special instructions m jmp @a this instruction sets the contents of a (accumulator) to pc (program counter) as the address, and causes a branch to that address. one of the n branch destination addresses is selected from a table, and then transferred to a. the instruction can be executed to perform n-branch processing. figure b.3-1 "jmp @a" shows a summary of the instruction. figure b.3-1 jmp @a m movw a, pc this instruction performs the operation which is the reverse of that performed by jmp @a. that is, the instruction stores the contents of pc in a. when the instruction is executed in the main routine, so that a specific subroutine is called, whether a contains a predetermined value can be checked by the subroutine. this can be used to determine that the branch source is not any unexpected section of the program and to check for program runaway. figure b.3-2 "movw a, pc" shows a summary of the instruction. figure b.3-2 movw a, pc after the movw a, pc instruction is executed, a contains the address of the operation code of the next instruction, rather than the address of the operation code of movw a, pc. accordingly, figure b.3-2 "movw a, pc" shows that a contains 1234 h , which is the address of the operation code of the instruction that follows movw a, pc. m mulu a this instruction performs an unsigned multiplication of al (lower eight bits of the accumulator) and tl (lower eight bits of the temporary accumulator), and stores the 16-bit result in a. the contents of t (temporary accumulator) do not change. the contents of ah (higher eight bits of the accumulator) and th (higher eight bits of the temporary accumulator) before execution of the instruction are not used for the operation. the instruction does not change the flags, and 1 2 3 4 h a x x x x h previous pc a current pc (before execution) (after execution) 1 2 3 4 h 1 2 3 4 h a a x x x x h 1 2 3 4 h 1 2 3 4 h 1 2 3 4 h previous pc current pc
519 appendix b overview of instructions therefore care must be taken when a branch may occur depending on the result of a multiplication. figure b.3-3 "mulu" shows a summary of the instruction. figure b.3-3 mulu m divu a this instruction divides the 16-bit value in t by the unsigned 8-bit value in al, and stores the 8- bit result and the 8-bit remainder in al and tl, respectively. a value of 0 is set to both ah and th. the contents of ah before execution of the instruction are not used for the operation. an unpredictable result is produced from data that results in more than eight bits. in addition, there is no indication of the result having more than eight bits. therefore, if it is likely that data will cause a result of more than eight bits, the data must be checked to ensure that the result will not have more than eight bits before it is used. the instruction does not change the flags, and therefore care must be taken when a branch may occur depending on the result of a division. figure b.3-4 "divu a" shows a summary of the instruction. figure b.3-4 divu a m xchw a, pc this instruction swaps the contents of a and pc, resulting in a branch to the address contained in a before execution of the instruction. after the instruction is executed, a contains the address that follows the address of the operation code of movw a, pc. this instruction is effective especially when it is used in the main routine to specify a table for use in a subroutine. figure b.3-5 "xchw a, pc" shows a summary of the instruction. figure b.3-5 xchw a, pc after the xchw a, pc instruction is executed, a contains the address of the operation code of the next instruction, rather than the address of the operation code of xchw a, pc. accordingly, figure b.3-5 "xchw a, pc" shows that a contains 1235 h , which is the address of the operation code of the instruction that follows xchw a, pc. this is why 1235 h is stored instead of 1234 h. 1 2 3 4 h a t 1 8 6 0 h a t (before execution) (after execution) 1 2 3 4 h 5 6 7 8 h 1 8 6 2 h a t 0 0 3 4 h a t (before execution) (after execution) 0 0 0 2 h 5 6 7 8 h 1 2 3 4 h a pc 1 2 3 5 h a pc (before execution) (after execution) 5 6 7 8 h 5 6 7 8 h
520 appendix b overview of instructions figure b.3-6 "example of using xchw a, pc" shows an assembly language example. figure b.3-6 example of using xchw a, pc m callv #vct this instruction is used to branch to a subroutine address stored in the vector table. the instruction saves the return address (contents of pc) in the location at the address contained in sp (stack pointer), and uses vector addressing to cause a branch to the address stored in the vector table. because callv #vct is a 1-byte instruction, the use of this instruction for frequently used subroutines can reduce the entire program size. figure b.3-7 "example of executing callv #3" shows a summary of the instruction. figure b.3-7 example of executing callv #3 after the callv #vct instruction is executed, the contents of pc saved on the stack area are the address of the operation code of the next instruction, rather than the address of the operation code of callv #vct. accordingly, figure b.3-7 "example of executing callv #3" shows that the value saved in the stack (1232 h and 1233 h ) is 5679 h , which is the address of the operation code of the instruction that follows callv #vct (return address). movw xchw db movw a, #putsub a, pc 'put out data', eol a, 1234 h (main routine) xchw a, ep pushw a mov a, @ep incw ep mov io, a cmp a, #eol bne pts1 popw a xchw a, ep jmp @a putsub pts1 (subroutine) output table data here 1 2 3 4 h pc sp f e d c h pc sp (before execution) (after execution) 1 2 3 2 h 5 6 7 8 h 1 2 3 2 h 1 2 3 3 h x x h x x h f e h d c h f f c 6 h f f c 7 h 1 2 3 2 h 1 2 3 3 h 5 6 h 7 9 h f e h d c h f f c 6 h f f c 7 h (-2)
521 appendix b overview of instructions b.4 bit manipulation instructions (setb, clrb) some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual. n read-modify-write operation by using these bit manipulation instructions, only the specified bit in a register or ram location can be set to 1 (setb) or cleared to 0 (clrb). however, as the cpu operates on data in 8-bit units, the actual operation (read-modify-write operation) involves a sequence of steps: 8-bit data is read, the specified bit is changed, and the data is written back to the location at the original address. table b.4-1 "bus operation for bit manipulation instructions" shows bus operation for bit manipulation instructions. n read operation upon the execution of bit manipulation instructions for some i/o ports and for the interrupt request flag bits, the value to be read differs between a normal read operation and a read-modify-write operation. m i/o ports (during a bit manipulation) from some i/o ports, an i/o pin value is read during a normal read operation, while an output latch value is read during a bit manipulation. this prevents the other output latch bits from being changed accidentally, regardless of the i/o directions and states of the pins. m interrupt request flag bits (during a bit manipulation) an interrupt request flag bit functions as a flag bit indicating whether an interrupt request exists during a normal read operation. however, 1 is always read from this bit during a bit manipulation. this prevents the flag from being cleared accidentally by a value of 0 which would otherwise be written to the interrupt request flag bit when another bit is manipulated. table b.4-1 bus operation for bit manipulation instructions code mnemonic to cycle address bus data bus rd wr rmw a0 to a7 clrb dir:b 4 1 n+1 dir 0 1 0 2 dir address data 0 1 1 a8 to af setb dir:b 3 dir address data 1 0 0 4 n+2 next instruction 0 1 0
522 appendix b overview of instructions b.5 f 2 mc-8l instructions table b.5-1 "transfer instructions" to table b.5-4 "other instructions" list the instructions used with the f 2 mc-8l. n transfer instructions table b.5-1 transfer instructions no. mnemonic ~ # operation tl th ah n z v c op code 1 mov dir, a 3 2 (dir)<--(a) - - - - - - - 45 2 mov @ix+off, a 4 2 ((ix)+off)<--(a) - - - - - - - 46 3 mov ext, a 4 3 (ext)<--(a) - - - - - - - 61 4 mov @ep, a 3 1 ((ep))<--(a) - - - - - - - 47 5 mov ri, a 3 1 (ri)<--(a) - - - - - - - 48 to 4f 6 mov a, #d8 2 2 (a)<--d8 al - - ++ --04 7 mov a, dir 3 2 (a)<--(dir) al - - ++ --05 8 mov a, @ix+off 4 2 (a)<--((ix)+off) al - - ++ --06 9 mov a, ext 4 3 (a)<--(ext) al - - ++ --60 10 mov a, @a 3 1 (a)<--((a)) al - - ++ --92 11 mov a, @ep 3 1 (a)<--((ep)) al - - ++ --07 12 mov a, ri 3 1 (a)<--(ri) al - - ++ - - 08 to 0f 13 mov dir, #d8 4 3 (dir)<--d8 - - - - - - - 85 14 mov @ix+off, #d8 5 3 ((ix)+off)<--d8 - - - - - - - 86 15 mov @ep, #d8 4 2 ((ep))<--d8 - - - - - - - 87 16 mov ri, #d8 4 2 (ri)<--d8 - - - - - - - 88 to 8f 17 movw dir, a 4 2 (dir)<--(ah), (dir+1)<--(al) - - - - - - - d5 18 movw @ix+off, a 5 2 ((ix)+off )<--(ah), ((ix)+off+1)<--(al) -------d6 19 movw ext, a 5 3 (ext)<--(ah), (ext+1)<--(al) - - - - - - - d4 20 movw @ep, a 4 1 ((ep))<--(ah), ((ep)+1)<--(al) -------d7 21 movw ep, a 2 1 (ep)<--(a) - - - - - - - e3 22 movw a, #d16 3 3 (a)<--d16 al ah dh ++ --e4 23 movw a, dir 4 2 (ah)<--(dir), (al)<--(dir+1) al ah dh ++ --c5
523 appendix b overview of instructions caution: in automatic transfer to t during byte transfer to a, al is transferred to tl. if an instruction has two or more operands, they are assumed to be saved in the order indicated by mnemonic. 24 movw a, @ix+off 5 2 (ah)<--((ix)+off), (al)<--((ix)+off+1) al ah dh ++ --c6 25 movw a, ext 5 3 (ah)<--(ext), (al)<--(ext+1) al ah dh ++ --c4 26 movw a, @a 4 1 (ah)<--((a)), (al)<--((a)+1) al ah dh ++ --93 27 movw a, @ep 4 1 (ah)<--((ep)), (al)<--((ep)+1) al ah dh ++ --c7 28 movw a, ep 2 1 (a)<--(ep) - - dh - - - - f3 29 movw ep, #d16 3 3 (ep)<--d16 - - - - - - - e7 30 movw ix, a 2 1 (ix)<--(a) - - - - - - - e2 31 movw a, ix 2 1 (a)<--(ix) - - dh - - - - f2 32 movw sp, a 2 1 (sp)<--(a) - - - - - - - e1 33 movw a, sp 2 1 (a)<--(sp) - - dh - - - - f1 34 mov @a, t 3 1 ((a))<--(t) - - - - - - - 82 35 movw @a, t 4 1 ((a))<--(th), ((a)+1)<--(tl) - - - - - - - 83 36 movw ix, #d16 3 3 (ix)<--d16 - - - - - - - e6 37 movw a, ps 2 1 (a)<--(ps) - - dh - - - - 70 38 movw ps, a 2 1 (ps)<--(a) - - - ++++ 71 39 movw sp, #d16 3 3 (sp)<--d16 - - - - - - - e5 40 swap 2 1 (ah)<-- -->(al) - - al - - - - 10 41 setb dir:b 4 2 (dir):b <--1 - - - - - - - a8 to af 42 clrb dir:b 4 2 (dir):b <--0 - - - - - - - a0 to a7 43 xch a, t 2 1 (al)<-- -->(tl) al - - - - - - 42 44 xchw a, t 3 1 (a)<-- -->(t) al ah dh - - - - 43 45 xchw a, ep 3 1 (a)<-- -->(ep) - - dh - - - - f7 46 xchw a, ix 3 1 (a)<-- -->(ix) - - dh - - - - f6 47 xchw a, sp 3 1 (a)<-- -->(sp) - - dh - - - - f5 48 movw a, pc 2 1 (a)<--(pc) - - dh - - - - f0 table b.5-1 transfer instructions (continued) no. mnemonic ~ # operation tl th ah n z v c op code
524 appendix b overview of instructions n arithmetic instructions table b.5-2 arithmetic operation instructions no. mnemonic ~ # operation tl th ah n z v c op code 1 addc a, ri 3 1 (a)<--(a)+(ri)+c - - - ++++ 28 to 2f 2 addc a, #d8 2 2 (a)<--(a)+d8+c - - - ++++ 24 3 addc a, dir 3 2 (a)<--(a)+(dir)+c - - - ++++25 4 addc a, @ix+off 4 2 (a)<--(a)+((ix)+off)+c - - - ++++ 26 5 addc a, @ep 3 1 (a)<--(a)+((ep))+c - - - ++++ 27 6 addcw a 3 1 (a)<--(a)+(t)+c - - dh ++++ 23 7 addc a 2 1 (al)<--(al)+(tl)+c - - - ++++ 22 8 subc a, ri 3 1 (a)<--(a)-(ri)-c - - - ++++ 38 to 3f 9 subc a, #d8 2 2 (a)<--(a)-d8-c - - - ++++ 34 10 subc a, dir 3 2 (a)<--(a)-(dir)-c - - - ++++ 35 11 subc a, @ix+off 4 2 (a)<--(a)-((ix)+off)-c - - - ++++ 36 12 subc a, @ep 3 1 (a)<--(a)-((ep))-c - - - ++++ 37 13 subcw a 3 1 (a)<--(t)-(a)-c - - dh ++++ 33 14 subc a 2 1 (al)<--(tl)-(al)-c - - - ++++ 32 15 inc ri 4 1 (ri)<--(ri)+1 - - - +++ -c8 to cf 16 incw ep 3 1 (ep)<--(ep)+1 - - - - - - - c3 17 incw ix 3 1 (ix)<--(ix)+1 - - - - - - - c2 18 incw a 3 1 (a)<--(a)+1 - - dh ++ --c0 19 dec ri 4 1 (ri)<--(ri)-1 - - - +++ -d8 to df 20 decw ep 3 1 (ep)<--(ep)-1 - - - - - - - d3 21 decw ix 3 1 (ix)<--(ix)-1 - - - - - - - d2 22 decw a 3 1 (a)<--(a)-1 - - dh ++ --d0 23 mulu a 19 1 (a)<--(al)x(tl) - - dh ----01 24 divu a 21 1 (a)<--(t)/(al), mod -->(t) dl 00 00 - - - - 11 25 andw a 3 1 (a)<--(a) (t) - - dh ++ r -63 26 orw a 3 1 (a)<--(a) (t) - - dh ++ r -73 27 xorw a 3 1 (a)<--(a) (t) - - dh ++ r -53 28 cmp a 2 1 (tl)-(al) - - - ++++ 12 29 cmpw a 3 1 (t)-(a) - - - ++++ 13 30 rorc a 2 1 --- ++ - + 03 c --> a
525 appendix b overview of instructions 31 rolc a 2 1 - - - ++ - + 02 32 cmp a, #d8 2 2 (a)-d8 - - - ++++ 14 33 cmp a, dir 3 2 (a)-(dir) - - - ++++ 15 34 cmp a, @ep 3 1 (a)-((ep)) --- ++++ 17 35 cmp a, @ix+off 4 2 (a)-((ix)+off) - - - ++++ 16 36 cmp a, ri 3 1 (a)-(ri) - - - ++++ 18 to 1f 37 daa 2 1 decimal adjust for addition - - - ++++ 84 38 das 2 1 decimal adjust for subtraction - - - ++++ 94 39 xor a 2 1 (a)<--(al) (tl) - - - ++ r - 52 40 xor a, #d8 2 2 (a)<--(al) d8 - - - ++ r -54 41 xor a, dir 3 2 (a)<--(al) (dir) - - - ++ r -55 42 xor a, @ep 3 1 (a)<--(al) ((ep)) - - - ++ r -57 43 xor a, @ix+off 4 2 (a)<--(al) ((ix)+off) - - - ++ r -56 44 xor a, ri 3 1 (a)<--(al) (ri) - - - ++ r - 58 to 5f 45 and a 2 1 (a)<--(al) (tl) - - - ++ r -62 46 and a, #d8 2 2 (a)<--(al) d8 - - - ++ r -64 47 and a, dir 3 2 (a)<--(al) (dir) - - - ++ r -65 48 and a, @ep 3 1 (a)<--(al) ((ep)) - - - ++ r -67 49 and a, @ix+off 4 2 (a)<--(al) ((ix)+off) - - - ++ r -66 50 and a, ri 3 1 (a)<--(al) (ri) - - - ++ r - 68 to 6f 51 or a 2 1 (a)<--(al) (tl) - - - ++ r -72 52 or a, #d8 2 2 (a)<--(al) d8 - - - ++ r -74 53 or a, dir 3 2 (a)<--(al) (dir) - - - ++ r -75 54 or a, @ep 3 1 (a)<--(al) ((ep)) - - - ++ r -77 55 or a, @ix+off 4 2 (a)<--(al) ((ix)+off) - - - ++ r -76 56 or a, ri 3 1 (a)<--(al) (ri) - - - ++ r - 78 to 7f 57 cmp dir, #d8 5 3 (dir)-d8 - - - ++++ 95 58 cmp @ep, #d8 4 2 ((ep))-d8 - - - ++++ 97 59 cmp @ix+off, #d8 5 3 ((ix)+off)-d8 - - - ++++ 96 60 cmp ri, #d8 4 2 (ri)-d8 - - - ++++ 98 to 9f 61 incw sp 3 1 (sp)<--(sp)+1 - - - - - - - c1 62 decw sp 3 1 (sp)<--(sp)-1 - - - - - - - d1 table b.5-2 arithmetic operation instructions (continued) no. mnemonic ~ # operation tl th ah n z v c op code c <-- a
526 appendix b overview of instructions n branch instructions table b.5-3 branch instructions no. mnemonic ~ # operation tl th ah n z v c op code 1 bz/beq rel 3 2 if z=1 then pc<--pc+rel - - - ---- fd 2 bnz/bne rel 3 2 if z=0 then pc<--pc+rel - - - ---- fc 3 bc/blo rel 3 2 if c=1 then pc<--pc+rel - - - ---- f9 4 bnc/bhs rel 3 2 if c=0 then pc<--pc+rel - - - ---- f8 5 bn rel 3 2 if n=1 then pc<--pc+rel - - - ---- fb 6 bp rel 3 2 if n=0 then pc<--pc+rel - - - ---- fa 7blt rel 32 if v n=1 then pc<--pc+rel - - - ---- ff 8bge rel 32 if v n=0 then pc<--pc+rel - - - ---- fe 9 bbc dir:b, rel 5 3 if (dir:b)=0 then pc<--pc+rel ---- + -- b0 to b7 10 bbs dir:b, rel 5 3 if (dir:b)=1 then pc<--pc+rel ---- + -- b8 to bf 11 jmp @a 2 1 (pc)<--(a) - - - ---- e0 12 jmp ext 3 3 (pc)<--ext - - - ---- 21 13 callv #vct 6 1 vector call - - - ---- e8 to ef 14 call ext 6 3 subroutine call - - - ---- 31 15 xchw a, pc 3 1 (pc)<--(a), (a)<--(pc)+1 -- dh ---- f4 16 ret 4 1 return from subroutine - - - ---- 20 17 reti 6 1 return from interrupt --- restore 30
527 appendix b overview of instructions n other instructions table b.5-4 other instructions no. mnemonic ~ # operation tl th ah n z v c op code 1pushw a 41 - - - ---- 40 2popw a 41 -- dh ---- 50 3pushw ix 41 - - - ---- 41 4 popw ix 4 1 - - - ---- 51 5nop 11 - - - ---- 00 6clrc 11 - - - --- r81 7setc 11 - - - --- s91 8clri 11 - - - ---- 80 9seti 11 - - - ---- 90
528 appendix b overview of instructions b.6 instruction map table b.6-1 "f 2 mc-8l instruction map" shows the f 2 mc-8l instruction map. n instruction map table b.6-1 f 2 mc-8l instruction map 0 1 2 3 4 5 6 7 8 9 a b c d e f nop mulu a rolc a rorc a mov a, #d8 mov a, dir mov a, @ix+d mov a, @ep mov a, r0 mov a, r1 mov a, r2 mov a, r3 mov a, r4 mov a, r5 mov a, r6 mov a, r7 swap divu a cmp a cmpw a cmp a, #d8 cmp a, dir cmp a, @ix+d cmp a, @ep cmp a, r0 cmp a, r1 cmp a, r2 cmp a, r3 cmp a, r4 cmp a, r5 cmp a, r6 cmp a, r7 ret jmp addr16 addc a addcw a addc a, #d8 addc a, dir addc a, @ix+d addc a, @ep addc a, r0 addc a, r1 addc a, r2 addc a, r3 addc a, r4 addc a, r5 addc a, r6 addc a, r7 reti call addr16 subc a subcw a subc a, #d8 subc a, dir subc a, @ix+d subc a, @ep subc a, r0 subc a, r1 subc a, r2 subc a, r3 subc a, r4 subc a, r5 subc a, r6 subc a, r7 pushw a pushw ix xch a, t xchw a, t mov dir, a mov @ix+d, a mov @ep, a mov r0, a mov r1, a mov r2, a mov r3, a mov r4, a mov r5, a mov r6, a mov r7, a popw a popw ix xor a xorw a xor a, #d8 xor a, dir xor a, @ix+d xor a, @ep xor a, r0 xor a, r1 xor a, r2 xor a, r3 xor a, r4 xor a, r5 xor a, r6 xor a, r7 mov a, ext mov ext, a and a andw a and a, #d8 and a, dir and a, @ix+d and a, @ep and a, r0 and a, r1 and a, r2 and a, r3 and a, r4 and a, r5 and a, r6 and a, r7 movw a, ps movw ps, a or a orw a or a, #d8 or a, dir or a, @ix+d or a, @ep or a, r0 or a, r1 or a, r2 or a, r3 or a, r4 or a, r5 or a, r6 or a, r7 clri clrc mov @a, t movw @a, t daa mov dir, #d8 mov @ix+d,#d8 mov @ep#, d8 mov r0, #d8 mov r1, #d8 mov r2, #d8 mov r3, #d8 mov r4, #d8 mov r5, #d8 mov r6, #d8 mov r7, #d8 seti setc mov a, @a movw a, @a das cmp dir, #d8 cmp @ix+d,#d8 cmp @ep#, d8 cmp r0, #d8 cmp r1, #d8 cmp r2, #d8 cmp r3, #d8 cmp r4, #d8 cmp r5, #d8 cmp r6, #d8 cmp r7, #d8 clrb dir : 0 clrb dir : 1 clrb dir : 2 clrb dir : 3 clrb dir : 4 clrb dir : 5 clrb dir : 6 clrb dir : 7 setb dir : 0 setb dir : 1 setb dir : 2 setb dir : 3 setb dir : 4 setb dir : 5 setb dir : 6 setb dir : 7 bbc dir : 0, rel bbc dir : 1, rel bbc dir : 2, rel bbc dir : 3, rel bbc dir : 4, rel bbc dir : 5, rel bbc dir : 6, rel bbc dir : 7, rel bbs dir : 0, rel bbs dir : 1, rel bbs dir : 2, rel bbs dir : 3, rel bbs dir : 4, rel bbs dir : 5, rel bbs dir : 6, rel bbs dir : 7, rel incw a incw sp incw ix incw ep movw a, ext movw a, dir movw a, @ix+d movw a, @ep inc r0 inc r1 inc r2 inc r3 inc r4 inc r5 inc r6 inc r7 decw a decw sp decw ix decw ep movw ext, a movw dir, a movw @ix+d, a movw @ep, a dec r0 dec r1 dec r2 dec r3 dec r4 dec r5 dec r6 dec r7 jmp @a movw sp, a movw ix, a movw ep, a movw a, #d16 movw sp, #d16 movw ix, #d16 movw ep, #d16 callv #0 callv #1 callv #2 callv #3 callv #4 callv #5 callv #6 callv #7 movw a, pc movw a, sp movw a, ix movw a, ep xchw a, pc xchw a, sp xchw a, ix xchw a, ep bnc rel bc rel bp rel bn rel bnz rel bz rel bge rel blt rel 0123456789abcdef l h
529 appendix c mask options appendix c mask options this appendix shows a list of mask options for the mb89570 series. n list of mask options table c-1 list of mask options no. model MB89577 mb89p579a mb89pv570 specification method to be specified when ordering a mask to be specified when ordering to be specified when ordering 1 selecting the initial value (*1) for the main clock oscillation stabilization wait time (fch = 10 mhz) ? 01: 2 14 /fch (approx. 1.63 ms) ? 10: 2 17 /fch (approx. 13.1 ms) ? 11: 2 18 /fch (approx. 26.2 ms) selectable 2 18 /fch (approx. 26.2 ms) 2 18 /fch (approx. 26.2 ms) *1: shall be used as the initial value upon reset for the oscillation stabilization wait time select bit of the system clock control register (sycc: wt1, wt0).
530 appendix d one-time prom and eprom microcontroller write specification appendix d one-time prom and eprom microcontroller write specification the mb89p579, equipped with the prom mode, allows a general-purpose rom programmer to write data using a dedicated adapter. n rom programmer adapters and recommended rom programmers the following shows rom programmer adapters and recommended rom programmers. ? contact information sun hayato co., ltd.: phone (81) 3-3986-0403 minato electronics co., ltd.: phone (81) 45-591-5611 writing data to the eprom 1. set the eprom programmer for the cu50-otp (device code: cdb86dc). 2. load the program data to the eprom programmer. 3. write data using the eprom programmer. table d-1 rom programmer adapters and recommended rom programmers package name applicable adapter model recommended programmer maker and programmer sun hayato co., ltd. minato electronics co., ltd. model1890a fpt-100p-m05 rom2-100lqf-32dp-8la under evaluation fpt-100p-m18 rom2-100tqf2-32dp-8la under evaluation
531 appendix e pin statuses of the mb89570 series appendix e pin statuses of the mb89570 series this appendix shows the pin statuses during various operations of the mb89570 series. n pin statuses during various operations table e-1 pin statuses during various operations pin name normal operation sleep mode stop mode spl=0 stop mode spl=1 during reset p80/into to p83/int3 port input-output/ resource input- output hold/external interrupt input hold/external interrupt input hi-z/external interrupt input hi-z x0, x0a oscillation input oscillation input hi-z hi-z oscillation input x1, x1a oscillation output oscillation output "h" output "h" output oscillation output moda mode input mode input mode input mode input mode input rst reset input-output reset input-output reset input-output reset input-output reset input-output p00 to p07 port input-output/ resource input- output hold/resource input-output hold hi-z hi-z p10/an4 to p17/an11 p20/to1 hold p23/to2 p21,p22,p24 to p27 hi-z p30/slc1 p31/sda1 p32/alert p33/scl2/uck3 p34/sda2/ui3 p35/uo3 p40/scl3/uck1 p41/sda3/ui1 p42/scl4/uck2 p43/sda4/ui2 p50/alr1 to p52/alr3 p53/aco p54/ofb1 to p56/ofb3 p70/dcin p71/dcin2 p72/vol1 p73/vsi1
532 appendix e pin statuses of the mb89570 series p74/vol2 port input-output/ resource input- output hold/resource input-output hold hi-z hi-z p75/vsi2 p76/vol3 p77/vsi3 p85/an0/sw1 to p87/an2/sw3 p90/an3 p91/da1 to p92/da2 p60/seg08 to p65/seg13/uo1 hi-z (*1) hi-z pb4/com0 to pb7/com3 "l" output pin pa0/seg00 to pa7/seg07 p84/ec port input/resource input hi-z pb0/v0 to pb3/v3 port output/ resource input hold/resource input hold/resource input hi-z (*1) resource input hi-z: high impedance spl: pin status specification bit of the standby control register (stbc) hold: the pin specified for output holds the pin status (level) immediately before the mode is entered. *1: hi-z does not occur while lcdc is selected. table e-1 pin statuses during various operations (continued) pin name normal operation sleep mode stop mode spl=0 stop mode spl=1 during reset
533 index index the index follows on the next page. this is listed in alphabetic order.
534 index index numerics 1/2 bias, 1/2 duty output waveform, example of... 479 1/3 bias, 1/3 duty output waveform, example of... 482 1/3 bias, 1/4 duty output waveform, example of... 485 16-bit data on ram, storage of .............................. 30 16-bit data on stack, storage of.............................. 31 16-bit operand, storage of ...................................... 30 16-bit timer/counter and vector table, register related to interrupts of ...................243 16-bit timer/counter, block diagram of .................. 236 16-bit timer/counter, block diagram of pin related to .................................................... 238 16-bit timer/counter, note on using....................... 249 16-bit timer/counter, pin related to ....................... 238 16-bit timer/counter, register related to ................ 239 8/16-bit timer/counter interrupt ............................. 218 8/16-bit timer/counter, block diagram of ............... 203 8/16-bit timer/counter, note on using.................... 229 8-bit receiving operation at operation mode 1 ......357 8-bit transmitting operation at operation mode 1.. 359 8-segment lcd panel and display data example (1/4 duty driving method), connection example of ................................................. 487 a a/d control register 1 (adc1)............................... 274 a/d control register 2 (adc2)............................... 276 a/d conversion function ....................................... 266 a/d conversion function, interrupt for ...................281 a/d conversion function, operation of .................. 283 a/d conversion function, program example of ..... 286 a/d conversion function, starting .........................282 a/d converter interrupt, register and vector table related to ........................................... 281 a/d converter, block diagram of........................... 267 a/d converter, note on using................................ 284 a/d data register (addh, addl) .........................278 a/d enable register 1 to 2 (aden1 to 2) .............. 279 acknowledge ................................................ 393, 433 address comparison enable register (wren)......500 addressing.................................................... 393, 433 adjusting brightness of lcd when internal dividing resistor is used.............................. 460 arbitration ..................................................... 394, 434 arithmetic instruction ............................................524 arithmetic operation result bit................................. 34 b battery 1 to 3 valid interrupt .............................. 327 baud rate generator reload register (src) .......... 344 bit manipulation instruction, read operation upon the execution of ................................ 521 block diagram of 8/16-bit timer/counter................ 203 block diagram of pin related to 8/16-bit timer/counter.............................................. 206 block diagram of pin related to i2c ...................... 371 block diagram of pin related to multi-address i2c....................................... 409 block diagram, i2c ............................................... 367 block diagram, multi-address i2c ........................ 405 branch instruction................................................. 526 bridge circuit......................................................... 442 bridge circuit block diagram ................................. 443 bridge circuit selection register 1 (brsr1) .......... 448 bridge circuit selection register 3 (brsr3) .......... 452 bridge circuit, block diagram of pin related to ...... 445 bridge circuit, pin related to.................................. 444 bridge circuit, registers related to......................... 447 bridge selection register 2 (brsr2) .................... 450 c clock controller, block diagram of........................... 62 clock generator ...................................................... 60 clock mode, operating state of ............................... 67 clock supply function.................................... 161, 186 clock supply function, operation of............... 167, 193 clock supply map ................................................... 58 clock timeout ................................................ 396, 436 comparator 1, voltage comparators 2 to 7 interrupt...................................................... 327 comparator 2 to 4 interrupt................................... 327 comparator block diagram ................................... 299 comparator control register 1 (cocr1) ............... 308 comparator control register 2 (cocr2) ............... 310 comparator input enable register (cier) ............. 325 comparator interrupt control register 1 (cicr1)... 315 comparator interrupt control register 2 (cicr2)... 319 comparator status register 1 (cosr1) ................ 312 comparator status register 2 (cosr2) ................ 317 comparator status register 3 (cosr3) ................ 321
535 index comparator status register 4 (cosr4) ................ 323 condition code register (ccr), structure of............ 34 continuous receiving operation ............................ 358 continuous transmission at operation mode 1 ..... 361 counter function ........................................... 202, 235 counter function mode, interrupt in ...................... 243 counter function, operation of ...................... 222, 246 counter function, program example of ................. 252 d d/a control register (dacr)................................. 294 d/a converter ....................................................... 290 d/a converter (da1, 2), block diagram of pin related to.................................................... 292 d/a converter (da1, 2), pin related to.................. 292 d/a converter block, block diagram of ................. 291 d/a converter operation ....................................... 296 d/a converter, register related to ......................... 293 d/a data register 1 and 2 (dadr1, 2) ................. 295 data setting register (wrdr)............................... 494 data timeout ................................................. 396, 436 data transfer................................................. 393, 433 dedicated register configuration............................. 32 dedicated register function..................................... 32 detecting start bit at receiving operation .............. 354 e error ............................................................. 399, 439 explanation of addressing .................................... 514 external dividing resistor ...................................... 461 external interrupt circuit, block diagram of ........... 257 external interrupt circuit, operation of................... 264 external interrupt control register (eic1) .............. 261 external interrupt function .................................... 256 external reset pin function...................................... 54 external reset pin, block diagram of ....................... 54 f fpt-100p-m05, package dimensions of................ 10 fpt-100p-m18, package dimension of ................. 11 function of i/o port ................................................. 88 function of register of port 0 ................................... 93 function of register of port 1 ................................... 98 function of register of port 2 ................................. 104 function of register of port 3 ................................. 111 function of register of port 4 ................................. 115 function of register of port 5 ................................. 119 function of register of port 6 ................................. 125 function of register of port 7..................................130 function of register of port 8..................................137 function of register of port 9..................................144 function of register of port a .................................150 function of register of port b .................................155 function of uart/sio ...........................................334 g gear function (function for switching speed of main clock) ...................................................68 general-purpose register area ................................28 general-purpose register, feature of .......................39 general-purpose register, structure of ....................38 i i/o circuit type.........................................................18 i/o map.................................................................504 i/o port, function of .................................................88 i/o port, program example of................................157 i2c address register (iadr) .................................381 i2c block diagram.................................................367 i2c bus control register (ibcr) ............................376 i2c bus status register (ibsr)..............................374 i2c clock control register (iccr) ..........................379 i2c data register (idar) .......................................382 i2c function ..........................................................364 i2c interface register, precaution in setting ..........395 i2c master timeout register (imto)......................389 i2c protocol ..........................................................392 i2c slave timeout register (isto) .........................390 i2c system............................................................392 i2c timeout clock register (itoc) .........................388 i2c timeout control register (itcr).......................383 i2c timeout data register (itod) ..........................387 i2c timeout status register (itsr) ........................385 i2c, block diagram of pin related to......................371 i2c, pin related to .................................................370 i2c, register and vector table address related to interrupt of ..................................391 i2c, register related to ..........................................372 instruction cycle (tinst) ............................................66 instruction map .....................................................528 internal dividing resistor........................................459 interrupt acceptance control bit ..............................36 interrupt at bus error .....................................391, 430 interrupt at data transfer completion.............391, 430 interrupt at timeout detection ........................391, 430 interrupt level setting register (ilr1, ilr2, ilr3, ilr4), structure of ...............................42
536 index interrupt processing................................................ 44 interrupt processing time ........................................ 47 interrupt request from peripheral function .............. 40 interrupt when external interrupt circuit is operating .................................................... 263 interrupt when interval timer function is active ..... 166 interrupt when interval timer function is active (watch interrupt) ......................................... 192 interval timer function ........................... 160, 200, 234 interval timer function (timebase timer), operation of ................................................ 167 interval timer function (watch interrupt) ................ 186 interval timer function (watch prescaler), operation of ................................................ 193 interval timer function mode, interrupt in .............. 243 interval timer function, operation of ...................... 244 interval timer function, program example of ......... 250 items in the instruction list .................................... 513 l lcd controller driver block diagram ..................... 457 lcd controller driver function............................... 456 lcd controller driver operation, explanation of .... 477 lcd controller driver, power supply voltage of..... 458 lcd display ram and output pin .........................475 lcd driving waveform .......................................... 478 lcd panel connection example and display data example (1/2 duty driving method)..... 481 lcd panel connection example and display data example (1/3 duty driving method)..... 484 lcdc control register 1 (lcr1) ........................... 466 lcdc control register 2 (lcr2) ........................... 469 lcdc control register 3 (lcr3) ........................... 471 lcdc control register 4 (lcr4) ........................... 473 low power consumption (standby) mode and when counter is suspended, operation in .. 248 lower address setting register (wrarl) .............. 498 m main clock mode, operation in ............................... 68 main clock oscillation stabilization delay time and reset source .......................................... 51 main clock, oscillation stabilization wait time of...... 70 mask option, list of ............................................... 529 master timeout ............................................. 397, 437 mb89570 series (fpt-100p-m05, fpt-100p-m18, mqp-100c-p02), pin assignment of .............. 9 mb89570 series, block diagram of ........................... 8 mb89570 series, feature ..........................................2 mb89570 series, product lineup in ........................... 5 memory access mode, selection of........................ 86 memory map .......................................................... 27 memory space, configuration of............................. 26 mode data .............................................................. 85 mode fetch ............................................................. 56 mode pin ................................................................ 56 mode pin (moda) .................................................. 85 mqp-100c-p02, package dimension of ................ 12 multi-address i2c address register (madr1 to 6)............................................. 419 multi-address i2c alert register (malr).......... 429 multi-address i2c block diagram ......................... 405 multi-address i2c bus control register (mbcr) ... 414 multi-address i2c bus status register (mbsr)..... 412 multi-address i2c clock control register (mccr). 417 multi-address i2c data register (mdar).............. 420 multi-address i2c function ................................... 402 multi-address i2c master timeout register (mmto) ..................................................... 427 multi-address i2c protocol ................................... 432 multi-address i2c slave timeout register (msto) ...................................................... 428 multi-address i2c system .................................... 432 multi-address i2c timeout clock register (mtoc)...................................................... 426 multi-address i2c timeout control register (mtcr) ...................................................... 421 multi-address i2c timeout data register (mtod)...................................................... 425 multi-address i2c timeout status register (mtsr) ...................................................... 423 multi-address i2c, block diagram of pin related to.................................................... 409 multi-address i2c, pin related to .......................... 408 multi-address i2c, register and vector table address related to interrupt of.................... 431 multi-address i2c, register related to................... 410 multiple interrupt .................................................... 46 n note on handling device ....................................... 24 note on using 16-bit timer/counter ....................... 249 note on using 8/16-bit timer/counter .................... 229 note on using timebase timer............................... 169 note on using watch prescaler ............................. 195 note on using watchdog timer .............................. 181 o operation in low power consumption (standby) mode and when counter is suspended ...... 248
537 index operation in main clock mode ................................ 68 operation in sleep mode......................................... 74 operation in stop mode .......................................... 75 operation in subclock and standby mode and when counter is suspended ....................... 228 operation in subclock mode ................................... 69 operation in watch mode........................................ 77 operation mode 0 of uart/sio, explanation of... 351 operation of a/d conversion function ................... 283 operation of clock supply function........................ 193 operation of counter function ....................... 222, 246 operation of external interrupt circuit.................... 264 operation of interval timer function............... 220, 244 operation of interval timer function (watch prescaler) ....................................... 193 operation of parallel discharge control ................. 329 operation of port 0.................................................. 94 operation of port 1................................................ 100 operation of port 2................................................ 106 operation of port 3................................................ 112 operation of port 4................................................ 116 operation of port 5................................................ 121 operation of port 6................................................ 127 operation of port 7................................................ 132 operation of port 8................................................ 139 operation of port 9................................................ 146 operation of port a ............................................... 151 operation of port b ............................................... 156 operation of square wave output initial setting function ...................................................... 225 operation of stopping and restarting 8/16-bit timer/counter.............................................. 227 operation of uart/sio ........................................ 350 operation of watch prescaler................................ 193 operation of watchdog timer................................. 179 oscillation stabilization delay reset state ................ 56 oscillation stabilization wait time ...................... 70, 84 oscillation stabilization wait time and timebase timer interrupt ............................. 166 oscillation stabilization wait time and watch interrupt ........................................... 192 oscillation stabilization wait time, selection of .......... 5 other instruction ................................................... 527 overview of f2mc-8l instruction ......................... 511 p parallel discharge control ..................................... 298 parallel discharge control, operation of ................ 329 pin associated with comparator ........................... 303 pin associated with comparator, block diagram of ..................................................304 pin description ........................................................13 pin related to 8/16-bit timer/counter......................205 pin related to a/d converter..................................270 pin related to a/d converter, block diagram of .....271 pin related to external interrupt circuit ..................258 pin related to external interrupt circuit, block diagram of ..................................................259 pin related to lcd controller driver.......................463 pin related to lcd controller driver , block diagram of ..................................................464 pin related to uart/sio.......................................337 pin related to uart/sio, block diagram of ..........338 pin state during reset ..............................................57 pin states after reading mode data .........................57 pinl status during various operation......................531 port 0, block diagram of ..........................................92 port 0, configuration of............................................91 port 0, operation of .................................................94 port 0, pin of............................................................91 port 1, block diagram of ..........................................97 port 1, configuration of............................................96 port 1, operation of ...............................................100 port 1, pin of............................................................96 port 1, register of ....................................................97 port 2, block diagram of ........................................103 port 2, configuration of..........................................102 port 2, operation of ...............................................106 port 2, pin of..........................................................102 port 2, register of ..................................................103 port 3, block diagram of ........................................109 port 3, configuration of..........................................108 port 3, operation of ...............................................112 port 3, pin of..........................................................108 port 3, register of ..................................................110 port 4, block diagram of ........................................114 port 4, configuration of..........................................113 port 4, operation of ...............................................116 port 4, pin of..........................................................113 port 4, register of ..................................................114 port 5, block diagram of ........................................118 port 5, configuration of..........................................117 port 5, operation of ...............................................121 port 5, pin of..........................................................117 port 5, register of ..................................................118 port 6, block diagram of ........................................124 port 6, configuration of..........................................123 port 6, operation of ...............................................127
538 index port 6, pin of .........................................................123 port 6, register of .................................................. 124 port 7, block diagram of........................................ 129 port 7, configuration of ......................................... 128 port 7, operation of ............................................... 132 port 7, pin of .........................................................128 port 8, block diagram of........................................ 135 port 8, configuration of ......................................... 134 port 8, operation of ............................................... 139 port 8, pins of ....................................................... 134 port 8, register of .................................................. 136 port 9, block diagram of........................................ 142 port 9, configuration of ......................................... 141 port 9, operation of ............................................... 146 port 9, pin of .........................................................141 port a, block diagram of ....................................... 149 port a, configuration of ......................................... 148 port a, operation of............................................... 151 port a, register of.................................................. 149 port b, block diagram of ....................................... 153 port b, configuration of ......................................... 152 port b, operation of............................................... 156 port b, pin of .........................................................152 port b, register of.................................................. 153 precaution in setting i2c interface register........... 395 precaution in setting multi-address i2c interface register ....................................................... 435 precaution in setting shift clock frequency....395, 435 precaution on priority at simultaneous writing.................................................395, 435 precaution on setting with software .............. 395, 435 r read-modify-write operation.................................. 521 receiving operation in clk asynchronous mode.. 353 reception error in clk asynchronous mode......... 354 reception interrupt ................................................ 349 register and vector table address related to interrupt of uart/sio ................................ 349 register and vector table associated with comparator interrupts ................................. 328 register and vector table related to interrupt of external interrupt circuit............263 register and vector table related to timebase timer interrupt ............................. 166 register and vector table related to watch prescaler interrupt............................ 192 register associated with comparator..................... 306 register bank pointer (rp), structure of .................. 37 register of port 0, function of .................................. 93 register of port 1, function of .................................. 98 register of port 2, function of ................................ 104 register of port 3, function of ................................ 111 register of port 4, function of ................................ 115 register of port 5, function of ................................ 119 register of port 6, function of ................................ 125 register of port 7, function of ................................ 130 register of port 8, function of ................................ 137 register of port 9, function of ................................ 144 register of port a, function of................................ 150 register of port b, function of................................ 155 register pdr0 and ddr0 of port 0 ........................ 92 register pdr7 and ddr7 of port 7 ...................... 129 register pdr9 and ddr9 of port 9 ...................... 143 register related to 8/16-bit timer/counter .............. 207 register related to a/d converter .......................... 273 register related to external interrupt circuit........... 260 register related to interrupt of 8/16-bit timer/counter and vector table ................... 219 register related to lcd controller driver ............... 465 register related to port 1......................................... 99 register related to port 3....................................... 111 register related to port 4....................................... 115 register related to port 6....................................... 126 register related to port 7....................................... 131 register related to port 8....................................... 138 register related to port 9....................................... 145 register related to port a ...................................... 150 register related to port b ...................................... 155 register related to uart/sio ............................... 339 reset flag register (rsfr) ...................................... 52 reset on ram content, effect of ............................. 56 reset operation, overview of................................... 55 reset source ........................................................... 50 rom programmer adapter and recommended rom programmer...................................... 530 s sample application ............................................... 331 sequential discharge control ................................ 298 sequential discharge control, operation of ........... 330 serial input data register (sidr)........................... 347 serial mode control register 1 (smc1) ................. 340 serial mode control register 2 (smc2) ................. 342 serial output data register (sodr)....................... 348 serial status and data register (ssd) ................... 345 setting with software, caution on.................. 395, 435 shift clock frequency, note on setting................... 435 shift clock frequency, precaution in setting .......... 395
539 index simultaneous writing, precaution on priority at ............................................ 395, 435 single chip mode .................................................... 85 slave timeout................................................ 398, 438 sleep mode, operation in........................................ 74 special instruction ................................................ 518 square wave output initial setting function, operation of................................................ 225 stack area for interrupt processing......................... 49 stack operation at interrupt return .......................... 48 stack operation at start of interrupt processing ...... 48 standby control register (stbc)............................. 78 standby mode ........................................................ 72 standby mode and interrupt, transition to............... 83 standby mode by interrupt, release of.................... 83 standby mode, operating state in........................... 73 standby mode, precaution in setting ...................... 84 start condition............................................... 393, 433 state transition diagram 1 (dual clock) ................... 80 stop condition............................................... 394, 434 stop mode, operation in ......................................... 75 stopping and restarting 8/16-bit timer/counter, operation of......................... 227 subclock and standby mode and when counter is suspended, operation in............ 228 subclock mode, operation in .................................. 69 subclock, oscillation stabilization wait time of ........ 71 symbols used with instruction .............................. 512 system clock control register (sycc), structure of................................................... 64 t timebase timer control register (tbtc)................ 164 timebase timer interrupt, oscillation stabilization wait time and.......................... 166 timebase timer, block diagram of ......................... 162 timebase timer, note on using.............................. 169 timebase timer, program example of ................... 171 time-based timer, operation of ............................. 167 timeout clock supply block ........................... 399, 439 timer 1 control register (t1cr) ............................ 208 timer 1 data register (t1dr) ................................ 214 timer 2 control register (t2cr) ............................ 211 timer 2 data register (t2dr).................................216 timer control register (tmcr) ...............................240 timer count register (tcr) ....................................242 transfer data format ..............................................352 transfer instruction ................................................522 transmission interrupt ...........................................349 transmitting operation in clk asynchronous mode ...................................355 u uart/sio operation mode, explanation of ..........356 uart/sio, block diagram of ................................335 uart/sio, function of ..........................................334 uart/sio, operation of........................................350 upper address setting register (wrarh) .............496 using external dividing resistor .............................462 using internal dividing resistor ..............................460 v various product and precaution for selecting productl, difference of.....................................7 vector table area.....................................................28 w watch mode, operation in .......................................77 watch prescaler control register (wpcr) .............190 watch prescaler, block diagram of ........................188 watch prescaler, note on using.............................195 watch prescaler, operation of ...............................193 watch prescaler, program example of ..................196 watchdog timer control register (wdtc) ..............177 watchdog timer function........................................174 watchdog timer, block diagram of.........................175 watchdog timer, note on using..............................181 watchdog timer, operation of ................................179 watchdog timer, program example of ...................182 wild register address, list of ..................................502 wild register application address ..........................490 wild register function.............................................490 wild register function operation, sequence of .......502 wild register function, block diagram of ................491 wild register function, register related to...............493
540 index
cm25-10140-1e fujitsu semiconductor ? controller manual f 2 mc-8l 8-bit microcontroller mb89570 series hardware manual february 2001 the first edition published fujitsu limited electronic devices edited technical communication dept.

fujitsu semiconductor f 2 mc-8l 8-bit microcontroller mb89570 series hardware manual

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